Philips Semiconductors
LPC2210/2220
16/32-bit ARM microcontrollers with external memory interface
Table 4:
Symbol
P3.19/A19
P3.20/A20
P3.21/A21
P3.22/A22
P3.23/A23/
XCLK
P3.24/CS3
P3.25/CS2
P3.26/CS1
P3.27/WE
Pin description
…continued
Pin (LQFP)
46
45
44
41
40
36
35
30
29
28
Pin (TFBGA) Type
L5
K5
N4
K4
N3
M2
M1
K2
K1
J4
O
O
O
O
O
O
O
O
O
O
O
I
27
J3
O
I
97
96
22
135
E13
F10
H2
C5
I
O
O
Description
A19 —
External memory address line 19.
A20 —
External memory address line 20.
A21 —
External memory address line 21.
A22 —
External memory address line 22.
A23 —
External memory address line 23.
XCLK —
Clock output.
CS3 —
LOW-active Chip Select 3 signal.
(Bank 3 addresses range 8300 0000 to 83FF FFFF)
CS2 —
LOW-active Chip Select 2 signal.
(Bank 2 addresses range 8200 0000 to 82FF FFFF)
CS1 —
LOW-active Chip Select 1 signal.
(Bank 1 addresses range 8100 0000 to 81FF FFFF)
WE —
LOW-active Write enable signal.
BLS3 —
LOW-active Byte Lane Select signal (Bank 3).
AIN7 —
A/D converter, input 7. This analog input is always
connected to its pin.
BLS2 —
LOW-active Byte Lane Select signal (Bank 2).
AIN6 —
A/D converter, input 6. This analog input is always
connected to its pin.
BLS1 —
LOW-active Byte Lane Select signal (Bank 1).
BLS0 —
LOW-active Byte Lane Select signal (Bank 0).
Not connected. This pin MUST NOT be pulled LOW or the
device might not operate properly.
External reset input:
A LOW on this pin resets the device,
causing I/O ports and peripherals to take on their default
states, and processor execution to begin at address 0. TTL
with hysteresis, 5 V tolerant.
Input to the oscillator circuit and internal clock generator
circuits.
Output from the oscillator amplifier.
Ground:
0 V reference.
P3.28/BLS3/
AIN7
P3.29/BLS2/
AIN6
P3.30/BLS1
P3.31/BLS0
n.c.
RESET
XTAL1
XTAL2
V
SS
142
141
3, 9, 26, 38,
54, 67, 79,
93, 103, 107,
111, 128
139
C3
B3
C2, E4, J2,
N2, N7, L10,
K12, F13,
D11, B13,
B11, D7
C4
I
O
I
V
SSA
I
Analog ground:
0 V reference. This should nominally be the
same voltage as V
SS
, but should be isolated to minimize noise
and error.
PLL analog ground:
0 V reference. This should nominally be
the same voltage as V
SS
, but should be isolated to minimize
noise and error.
1.8 V core power supply:
This is the power supply voltage
for internal circuitry.
V
SSA(PLL)
138
B4
I
V
DD(1V8)
37, 110
N1, A12
I
9397 750 14061
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02— 30 May 2005
12 of 49
PHILIPS [ NXP SEMICONDUCTORS ]
