引脚配置
100
64
48
Pin Name
默认值
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP LQFP QFN
27
18
—
DAC0_OUT/
ADC0_SE23
DAC0_OUT/
ADC0_SE23
DAC0_OUT/
ADC0_SE23
28
29
30
31
32
19
20
21
—
—
14
15
16
—
—
XTAL32
EXTAL32
VBAT
XTAL32
XTAL32
EXTAL32
VBAT
EXTAL32
VBAT
PTE24
PTE25
ADC0_SE17
ADC0_SE18
ADC0_SE17
ADC0_SE18
PTE24
CAN1_TX
CAN1_RX
TPM0_CH0
TPM0_CH1
I2S1_TX_FS
LPI2C0_SCL
LPI2C0_SDA
EWM_OUT_b
EWM_IN
PTE25
I2S1_TX_
BCLK
33
34
35
36
37
38
39
—
22
23
24
25
26
27
—
17
18
19
20
21
—
PTE26/
CLKOUT32K
DISABLED
PTE26/
CLKOUT32K
I2S1_TXD0
RTC_
CLKOUT
USB_CLKIN
PTA0
PTA1
PTA2
PTA3
JTAG_TCLK /
SWD_CLK
PTA0
PTA1
PTA2
PTA3
UART0_CTS_ TPM0_CH5
b
EWM_IN
JTAG_TCLK /
SWD_CLK
JTAG_TDI
UART0_RX
CMP0_OUT
LPI2C1_
HREQ
TPM1_CH1
TPM1_CH0
JTAG_TDI
JTAG_TDO /
TRACE_SWO
UART0_TX
JTAG_TDO /
TRACE_SWO
JTAG_TMS /
SWD_DIO
UART0_RTS_ TPM0_CH0
b
EWM_OUT_b
JTAG_TMS /
SWD_DIO
PTA4/
LLWU_P3
NMI_b
PTA4/
LLWU_P3
TPM0_CH1
I2S0_MCLK
NMI_b
PTA5
DISABLED
PTA5
USB_CLKIN
TPM0_CH2
I2S0_TX_
BCLK
JTAG_TRST_
b
40
41
42
43
—
—
28
29
—
—
—
—
VDD
VDD
VDD
VSS
VSS
VSS
PTA12
DISABLED
DISABLED
PTA12
CAN0_TX
CAN0_RX
TPM1_CH0
TPM1_CH1
I2S0_TXD0
PTA13/
PTA13/
I2S0_TX_FS
LLWU_P4
LLWU_P4
44
—
—
PTA14
DISABLED
PTA14
SPI0_PCS0
UART0_TX
I2S0_RX_
BCLK
45
46
—
—
—
—
PTA15
PTA16
DISABLED
DISABLED
PTA15
PTA16
SPI0_SCK
UART0_RX
I2S0_RXD0
SPI0_SOUT
UART0_CTS_
b
I2S0_RX_FS
47
—
—
PTA17
DISABLED
PTA17
SPI0_SIN
UART0_RTS_
b
I2S0_MCLK
48
49
50
51
30
31
32
33
22
23
24
25
VDD
VDD
VDD
VSS
VSS
VSS
PTA18
PTA19
EXTAL0
XTAL0
EXTAL0
XTAL0
PTA18
PTA19
TPM_CLKIN0
TPM_CLKIN1
LPTMR0_
ALT1
52
53
34
35
26
27
RESET_b
RESET_b
RESET_b
PTB0/
LLWU_P5
ADC0_SE8
ADC0_SE8
PTB0/
LLWU_P5
LPI2C0_SCL
LPI2C0_SDA
TPM1_CH0
TPM1_CH1
FXIO0_D4
FXIO0_D5
UART0_RX
UART0_TX
54
36
28
PTB1
ADC0_SE9
ADC0_SE9
PTB1
EWM_IN
29
KS22/KS20 Microcontroller, Rev 3, 04/2016
NXP Semiconductor, Inc.
NXP [ NXP ]
