ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
Table 34: DMA Configuration register: bit description…continued
Bit[1]
Symbol
Description
3 to 2
MODE[1:0]
These bits only affect the GDMA (slave) and MDMA (master)
handshake signals:
00H — DIOR (master) or DIOW (slave): strobes data from the
DMA bus into the ISP1581; DIOW (master) or DIOR (slave):
puts data from the ISP1581 on the DMA bus
01H — DIOR (master) or DACK (slave) strobes the data from
the DMA bus into the ISP1581; DACK (master) or DIOR
(slave) puts the data from the ISP1581 on the DMA bus
02H — DACK (master and slave) strobes the data from the
DMA bus into the ISP1581 and also puts the data from the
ISP1581 on the DMA bus (This mode is applicable only to
16-bit DMA; this mode cannot be used for 8-bit DMA.)
03H — reserved.
1
0
-
reserved
WIDTH
This bit selects the DMA bus width for GDMA (slave) and
MDMA (master):
0 — 8-bit data bus
1 — 16-bit data bus.
[1] The DREQ pin will be driven only after you perform a write access to the DMA Configuration register.
That is, after you have configured the DMA Configuration register.
[2] DREQ is asserted only if space (writing) or data (reading) is available in the FIFO.
[3] This process is stopped when the transfer FIFO becomes empty.
[4] PIO Read or Write that started using DMA Command Register only performs 16-bit transfer.
9.4.4 DMA Hardware register (address: 3CH)
The DMA Hardware register consists of 1 byte. The bit allocation is shown in
Table 35.
This register determines the polarity of the bus control signals (EOT, DACK, DREQ,
DIOR, DIOW) and the DMA mode (master or slave). It also controls whether the
upper and lower parts of the data bus are swapped (bits ENDIAN[1:0]), for modes
GDMA (slave) and MDMA (master) only.
Table 35: DMA Hardware register: bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
ENDIAN[1:0]
EOT_
POL
MASTER
ACK_
POL
DREQ_
POL
WRITE_
POL
READ_
POL
Reset
00H
00H
R/W
0
0
0
0
0
0
1
1
0
0
0
0
Bus reset
Access
R/W
R/W
R/W
R/W
R/W
R/W
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© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
35 of 79
NXP [ NXP ]
