ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
Table 2:
Pin description for LQFP64 …continued
Symbol[1]
Pin
Type[2] Description
READY/
IORDY
22
I/O
Generic processor mode: ready signal (READY; output)
A LOW level signals that ISP1581 is processing a previous
command or data and is not ready for the next command or
data transfer; a HIGH level signals that ISP1581 is ready
for the next microprocessor read or write.
Split Bus mode: DMA ready signal (IORDY; input); used
for accessing ATA/ATAPI peripherals (PIO and UDMA
modes only).
bidirectional pad; push pull output; 5 ns slew rate control;
TTL; 5 V tolerant.
DGND
23
24
-
-
digital ground
[3]
VCC(3.3)
supply voltage (3.3 V ± 0.3 V); supplies internal digital
circuits or it is the tapped out voltage from the internal
regulator; this regulated voltage cannot be used to drive
external devices; see Section 10
CS
25
26
I
I
chip select input; TTL; 5 V tolerant.
(R/W)/RD
input; function is determined by input MODE0 at power-up:
MODE0 = 0 — pin functions as R/W (Motorola style)
MODE0 = 1 — pin functions as RD (8051 style).
input pad; TTL with hysteresis; 5 V tolerant.
DS/WR
27
I
input; function is determined by input MODE0 at power-up:
MODE0 = 0 — pin functions as DS (Motorola style)
MODE0 = 1 — pin functions as WR (8051 style).
input pad; TTL with hysteresis; 5 V tolerant.
INT
28
29
O
I
interrupt output; programmable polarity (active HIGH or
LOW) and signaling (edge or level triggered)
CMOS output; 5 ns slew rate control.
ALE/A0
input; function determined by input MODE1 during
power-up:
MODE1 = 0 — pin functions as ALE (address latch
enable); a falling edge latches the address on the
multiplexed address/data bus (AD[7:0])
MODE1 = 1 — pin functions as A0 (address/data selection
on AD[7:0]); a logic 1 detected on the rising edge of the
WR pulse qualifies AD[7:0] as a register address; a logic 0
detected on the rising edge of the WR pulse qualifies
AD[7:0] as a register data; used in Split Bus mode only.
Remark: Connect to DGND in the Generic Processor
mode.
input pad; TTL; 5 V tolerant.
AD0
30
I/O
bit 0 of multiplexed address/data.
bidirectional pad; push pull output; 5 ns slew rate control;
TTL; 5 V tolerant.
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
7 of 79
NXP [ NXP ]
