ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
Table 2:
Pin description for LQFP64 …continued
Symbol[1]
Pin
Type[2] Description
DIOR
14
I/O
DMA read strobe (programmable polarity); direction
depends on bit MASTER in the DMA Hardware register
(DMA slave: input, DMA master: output); see Table 35 and
Table 36; when not in use, connect this pin to VCC(I/O)
through a 10 kΩ resistor
bidirectional pad; push pull output; 5 ns slew rate control;
TTL; 5 V tolerant.
DIOW
15
I/O
DMA write strobe (programmable polarity); direction
depends on bit MASTER in the DMA Hardware register
(DMA slave: input, DMA master: output); see Table 35 and
Table 36; when not in use, connect this pin to VCC(I/O)
through a 10 kΩ resistor
bidirectional pad; push pull output; 5 ns slew rate control;
TTL; 5 V tolerant.
INTRQ
CS1[5]
CS0[5]
16
17
18
19
I
interrupt request input from ATA/ATAPI peripheral
input pad; TTL with hysteresis; 5 V tolerant; internal
pull-down resistor.
O
O
I/O
chip select output for ATA/ATAPI device; see Table 33 and
Table 34
CMOS output; 5 ns slew rate control
chip select output for ATA/ATAPI device; see Table 33 and
Table 34
CMOS output; 5 ns slew rate control
BUS_CONF/
DA0[5]
during power-up: input to select the bus configuration;
see Table 33 and Table 34
0 — Split Bus mode; multiplexed 8-bit address/data bus on
AD[7:0], separate DMA data bus on DATA[15:0][4]
1 — Generic Processor mode; separate 8-bit address on
AD[7:0], 16-bit processor data bus on DATA[15:0]. DMA is
multiplexed on the processor bus as DATA[15:0].
normal operation: address output to select the task file
register of an ATA/ATAPI device.
bidirectional pad; push pull output; 5 ns slew rate control;
TTL; 5 V tolerant
MODE0
DA1[5]
20
I/O
during power-up: input to select the read/write strobe
functionality in generic processor mode; see Table 33 and
Table 34
0 — Motorola style: pin 26 is R/W and pin 27 is DS
1 — 8051 style: pin 26 is RD and pin 27 is WR
normal operation: address output to select the task file
register of an ATA/ATAPI device
bidirectional pad; push pull output; 5 ns slew rate control;
TTL; 5 V tolerant
DA2[5]
21
O
address output to select the task file register of an
ATA/ATAPI device; see Table 33 and Table 34
CMOS output; 5 ns slew rate control
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
6 of 79
NXP [ NXP ]
