ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
(2)
DREQ
t
t
d1
t
t
h1
T
su1
w1
cy1
(1)
(1)
DACK
t
w2
t
d2
HIGH
DIOR/DIOW
t
h2
[
]
]
(read) DATA 15:0
t
t
su2
h3
[
(write) DATA 15:0
MGT503
DREQ is asserted for every transfer.
Data strobe: DACK (read/write).
(1) Programmable polarity: shown as active LOW.
(2) Programmable polarity: shown as active HIGH.
Fig 24. GDMA slave mode timing (BURST = 01H, MODE = 02H).
t
(2)
(1)
(1)
su1
DREQ
DACK
t
t
h1
t
w1
w2
t
su3
t
t
T
d1
cy1
d2
DIOR/DIOW
t
h2
[
]
(read) DATA 15:0
t
t
h3
su2
[
]
(write) DATA 15:0
MGT504
DREQ is asserted once per N transfers (N is determined by the BURST value). Example shown here: N = 2.
Data strobes: DIOR (read), DIOW (write).
(1) Programmable polarity: shown as active LOW.
(2) Programmable polarity: shown as active HIGH.
Fig 25. GDMA slave mode timing (BURST > 01H, MODE = 00H).
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
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