ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
Table 77: PIO mode timing parameters…continued
VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = −40 to +85 °C.
Symbol Parameter
Mode 0
Mode 1
Mode 2
Mode 3
Mode 4
Unit
tsu3(min)
data set-up time before DIOR on
(minimum)
50
35
20
20
20
ns
th3(min.)
td2(max)
data hold time after DIOR off (minimum)
5
5
5
5
5
ns
ns
[2]
data to three-state delay after DIOR off
(minimum)
30
30
30
30
30
th1(min)
tsu4(min)
tsu5(min)
tw3(max)
address hold time after DIOR/DIOW off
(minimum)
20
15
10
10
10
ns
ns
ns
ns
[3]
[3]
IORDY after DIOR/DIOW on set-up time
(minimum)
35
35
35
35
35
read data to IORDY HIGH set-up time
(minimum)
0
0
0
0
0
IORDY LOW pulse width (maximum)
1250
1250
1250
1250
1250
[1] Tcy1 is the total cycle time, consisting of the command active time tw1and is the command recovery (= inactive) time tw2: Tcy1 = tw1 + tw2
The minimum timing requirements for Tcy1, tw1 and tw2 must all be met. Since Tcy1(min) is greater than the sum of tw1(min) and tw2(min), a
host implementation must lengthen tw1 and/or tw2 to ensure that Tcy1 is equal to or greater than the value reported in the IDENTIFY
DEVICE data. A device implementation shall support any legal host implementation.
.
[2] td2 specifies the time after DIOR is negated, when the data bus is no longer driven by the device (three-state).
[3] If IORDY is LOW at tsu4, the host waits until IORDY is made HIGH before the PIO cycle is completed. In that case, tsu5 must be met for
reading (tsu3 does not apply). When IORDY is HIGH at tsu4, tsu3 must be met for reading (tsu5 does not apply).
14.2.2 GDMA slave mode
(2)
DREQ
t
su1
t
t
h1
T
w1
cy1
(1)
(1)
DACK
t
t
d1
su3
DIOR/DIOW
t
w2
t
a1
t
t
d2
h2
[
]
]
(read) DATA 15:0
t
t
h3
su2
[
(write) DATA 15:0
MGT500
DREQ is continuously asserted until the last transfer is done or the FIFO is full.
Data strobes: DIOR (read), DIOW (write).
(1) Programmable polarity: shown as active LOW.
(2) Programmable polarity: shown as active HIGH.
Fig 21. GDMA slave mode timing (BURST = 00H, MODE = 00H).
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
61 of 79
NXP [ NXP ]
