ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
Table 79: MDMA mode timing parameters…continued
VCC = 4.0 to 5.5 V; VGND = 0 V; Tamb = −40 to +85 °C.
Symbol
Parameter
Mode 0 Mode 1 Mode 2 Unit
tsu2(min)
data set-up time before DIOR/DIOW off 100
(minimum)
30
20
ns
th2(min)
data hold time after DIOW off (minimum) 20
15
0
10
0
ns
ns
tsu1(min)
DACK set-up time before DIOR/DIOW on
(minimum)
0
th1(min)
tw2(min)
DACK hold time after DIOR/DIOW off
(minimum)
DIOR recovery time (minimum)[1]
DIOW recovery time (minimum)[1]
20
5
5
ns
50
50
50
40
40
25
25
25
35
35
25
ns
ns
ns
ns
ns
215
td2(max)
DIOR on to DREQ off delay (maximum) 120
DIOW on to DREQ off delay (maximum) 40
td3(max)
DACK off to data lines three-state delay 20
(maximum)
[1] Tcy1 is the total cycle time, consisting of the command active time tw1 and is the command recovery
(= inactive) time tw2: Tcy1 = tw1 + tw2. The minimum timing requirements for Tcy1, tw1 and tw2 must all
be met. Since Tcy1(min) is greater than the sum of tw1(min) and tw2(min), a host implementation must
lengthen tw1 and/or tw2 to ensure that Tcy1 is equal to or greater than the value reported in the
IDENTIFY DEVICE data. A device implementation shall support any legal host implementation.
14.2.4 UDMA mode
T
T
cy1
cy1
t
t
su1
su1
(1)
(1)
DIOR
(sender)
t
t
t
h1
h1
h1
[
]
DATA 15:0
(sender)
t
t
t
t
su2
t
h2
su2
h2
h2
(1)
(1)
IORDY
(receiver)
(receiver)
[
]
DATA 15:0
MGT507
(1) DATA[15:0] and strobe signals at the receiver require some time to stabilize due to the settling time and propagation delay
of the cable.
Fig 30. UDMA timing: sustained synchronous burst.
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
66 of 79
NXP [ NXP ]
