ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
8. Modes of operation
The ISP1581 has two bus configuration modes, selected via pin BUS_CONF/DA0 at
power-up:
• Split Bus mode (BUS_CONF = 0): 8-bit multiplexed address/data bus and
separate 8-bit/16-bit DMA bus
• Generic Processor mode (BUS_CONF = 1); separate 8-bit address and 16-bit
data bus
Details of the bus configurations for each mode are given in Table 3. Typical interface
circuits for each mode are given in Section 15.
Table 3:
Bus configuration modes
BUS_CONF PIO width
DMA width
Description
DMAWD = 0 DMAWD = 1
0
1
AD[7:0]
D[7:0]
D[15:0]
Split Bus mode: multiplexed address/data on pins AD[7:0];
separate 8/16-bit DMA bus on pins DATA[15:0]
A[7:0]
D[7:0]
D[15:0]
Generic Processor mode: separate 8-bit address on pins
D[15:0]
AD[7:0]; 16-bit data (PIO and DMA) on pins DATA[15:0]
9. Register descriptions
Table 4:
Name
Register overview
Destination
Address
(Hex)
Description
Size
(bytes)
Initialization registers
Address
device
device
00
USB device address + enable
1
1
Mode
0C
power-down options, global interrupt
enable, SoftConnect
Interrupt Configuration
device
10
interrupt sources, trigger mode, output
polarity
1
Interrupt Enable
DMA Configuration
DMA Hardware
Data flow registers
Endpoint Index
Control Function
Data Port
device
14
38
3C
interrupt source enabling
4
2
1
DMA controller
DMA controller
see sub-section “DMA registers”
see sub-section “DMA registers”
endpoints
endpoint
endpoint
endpoint
endpoint
endpoint
2C
28
20
1C
04
08
endpoint selection, data flow direction
endpoint buffer management
data access to endpoint FIFO
packet size counter
1
1
2
2
2
2
Buffer Length
Endpoint MaxPacketSize
Endpoint Type
maximum packet size
selects endpoint type: control,
isochronous, bulk or interrupt
Short Packet
endpoint
24
short packet received on OUT endpoint
2
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
16 of 79
NXP [ NXP ]
