ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
7.8 DMA Interface and DMA Handler
The DMA block can be subdivided into two blocks: the DMA Handler and the DMA
Interface.
The firmware writes to the DMA Command register to start a DMA transfer (see
Table 28). The command opcode determines whether a generic DMA, PIO, MDMA or
UDMA transfer will start. The Handler interfaces to the same FIFO (internal RAM) as
used by the USB core. Upon receiving the DMA Command, the DMA Handler directs
the data from the internal RAM to the external DMA device or from the external DMA
device to the internal RAM.
The DMA Interface configures the timings and the DMA handshake. Data can be
transferred either using DIOR and DIOW strobes or by the DACK and DREQ
handshakes. The different DMA configurations are set up by writing to the DMA
Configuration register (see Table 33 and Table 34).
For an IDE-based storage interface, the applicable DMA modes are PIO (Parallel
I/O), MDMA (Multi word DMA; ATA), and UDMA (Ultra DMA; ATA).
For a generic DMA interface, the DMA modes that can be used are Generic DMA
(Slave) and MDMA (Master).
7.9 Power-on reset
The ISP1581 requires a minimum pulse width of 500 µs.
The RESET pin can be either connected to VCC(3.3) using the internal POR circuit or
externally controlled by the microcontroller, ASIC, and so on. When VCC(3.3) is directly
connected to the RESET pin, the internal pulse width tPORP will be typically 200 ns.
The power-on reset function can be explained by viewing the dips at t2–t3 and t4–t5
on the VCC(3.3) curve (Figure 3).
t0 — The internal POR starts with a HIGH level.
t1 — The detector will see the passing of the trip level and a delay element will add
another tPORP before it drops to LOW.
t2-t3 — The internal POR pulse will be generated whenever VCC(3.3) drops below Vtrip
for more than 11 µs.
t4-t5 — The dip is too short (< 11 µs) and the internal POR pulse will not react and
will remain LOW.
V
CC(3.3)
V
trip
t4
t0
t1
t
t3
t5
t2
(1)
PORP
t
PORP
PORP
004aaa682
(1) PORP = power-on reset pulse.
Fig 3. POR timing.
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
14 of 79
NXP [ NXP ]
