ISP1581
Hi-Speed USB peripheral controller
Philips Semiconductors
• DDBGMODOUT[1:0]: interrupts for the DATA OUT endpoints 1 to 7.
The Debug mode settings for CDBGMOD, DDBGMODIN and DDBGMODOUT allow
the user to individually configure when the ISP1581 will send an interrupt to the
external microprocessor. Table 11 lists the available combinations.
Bit INTPOL controls the signal polarity of the INT output (active HIGH or LOW, rising
or falling edge). For level-triggering bit INTLVL must be made logic 0. By setting
INTLVL to logic 1 an interrupt will generate a pulse of 60 ns (edge-triggering).
Table 9:
Bit
Interrupt Configuration register: bit allocation
7
6
5
4
3
2
1
INTLVL
0
0
INTPOL
0
Symbol
Reset
CDBGMOD[1:0]
DDBGMODIN[1:0]
DDBGMODOUT[1:0]
03H
03H
R/W
03H
03H
R/W
03H
03H
R/W
Bus reset
Access
unchanged unchanged
R/W R/W
Table 10: Interrupt Configuration register: bit description
Bit
Symbol
Description
7 to 6
5 to 4
3 to 2
1
CDBGMOD[1:0]
DDBGMODIN[1:0]
Control 0 Debug Mode: values see Table 11
Data Debug Mode IN: values see Table 11
DDBGMODOUT[1:0] Data Debug Mode OUT: values see Table 11
INTLVL
Interrupt Level: selects the signaling mode on output
INT (0 = level, 1 = pulsed). In pulsed mode an interrupt
produces a 60 ns pulse. Bus reset value: unchanged.
0
INTPOL
Interrupt Polarity: selects signal polarity on output INT
(0 = active LOW, 1 = active HIGH). Bus reset value:
unchanged.
Table 11: Debug mode settings
Value
CDBGMOD
DDBGMODIN
DDBGMODOUT
00H
Interrupt on all ACK and
NAK
Interrupt on all ACK
and NAK
Interrupt on all ACK, NYET
and NAK
01H
1XH
Interrupt on all ACK.
Interrupt on ACK
Interrupt on ACK and NYET
Interrupt on all ACK and
first NAK[1]
Interrupt on all ACK
and first NAK[1]
Interrupt on all ACK, NYET
and first NAK[1]
[1] First NAK: the first NAK on an IN or OUT token after a previous ACK response.
9.2.4 Interrupt Enable register (address: 14H)
This register enables/disables individual interrupt sources. The interrupt for each
endpoint can be individually controlled via the associated IEPnRX or IEPnTX bits (‘n’
representing the endpoint number). All interrupts can be globally disabled via bit
GLINTENA in the Mode Register (see Table 7).
An interrupt is generated when the USB SIE receives or generates an ACK or NAK
on the USB bus. The interrupt generation depends on the Debug mode settings of bit
fields CDBGMOD, DDBGMODIN and DDBGMODOUT.
9397 750 13462
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 23 December 2004
20 of 79
NXP [ NXP ]
