NXP Semiconductors
HEF4081B
Quad 2-input AND gate
11. Waveforms
Measurement points are given in
Logic levels: V
OL
and V
OH
are typical output voltage levels that occur with the output load.
Fig 4.
Table 9.
V
DD
Input to output propagation delay and output transition times
Measurement points
Input
V
M
0.5V
DD
Output
V
M
0.5V
DD
Supply voltage
5 V to 15 V
Test data is given in
Definitions for test circuit:
DUT = Device Under Test.
C
L
= load capacitance including jig and probe capacitance.
R
T
= termination resistance should be equal to the output impedance Z
o
of the pulse generator.
Fig 5.
Table 10.
V
DD
Test circuit for measuring switching times
Test data
Input
V
I
V
SS
or V
DD
t
r
, t
f
20 ns
Load
C
L
50 pF
Supply voltage
5 V to 15 V
HEF4081B
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© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 8 — 15 December 2015
6 of 11
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