HEF4051B
NXP Semiconductors
8-channel analog multiplexer/demultiplexer
t
W
V
I
90 %
negative
pulse
V
V
V
M
M
10 %
0 V
t
t
r
f
t
t
f
r
V
I
90 %
M
positive
pulse
V
M
10 %
0 V
t
W
V
V
DD
V
V
I
DD
V
I
S1
O
R
L
PULSE
GENERATOR
open
DUT
R
T
C
L
V
V
SS
EE
001aaj903
Test data is given in Table 10.
Definitions:
DUT = Device Under Test.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including test jig and probe.
RL = Load resistance.
Fig 16. Test circuit for measuring switching times
Table 10. Test data
Input
Yn, Z
Load
CL
S1 position
[1]
Sn and E tr, tf
VM
RL
tPHL
tPLH
tPZH, tPHZ tPZL, tPLZ other
VEE VDD VEE
VDD or VEE VDD or VSS 20 ns
0.5VDD
50 pF
10 k
VDD or VEE VEE
[1] For Yn to Z or Z to Yn propagation delays use VEE. For Sn to Yn or Z propagation delays use VDD
.
HEF4051B
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© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 10 — 17 November 2011
12 of 23
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