NXP Semiconductors
HEF4051B-Q100
8-channel analog multiplexer/demultiplexer
6. Pinning information
6.1 Pinning
HEF4051B-Q100
Y4
Y6
Z
Y7
Y5
E
V
EE
V
SS
1
2
3
4
5
6
7
8
aaa-003493
16 V
DD
15 Y2
14 Y1
13 Y0
12 Y3
11 S1
10 S2
9
S3
1
2
3
4
5
6
7
8
aaa-003494
HEF4051B-Q100
Y4
Y6
Z
Y7
Y5
E
V
EE
V
SS
16 V
DD
15 Y2
14 Y1
13 Y0
12 Y3
11 S1
10 S2
9
S3
Fig 6.
Pin configuration SOT109-1
Fig 7.
Pin configuration SOT403-1
6.2 Pin description
Table 2.
Symbol
E
V
EE
V
SS
S1, S2, S3
Z
V
DD
Pin description
Pin
6
7
8
11, 10, 9
3
16
Description
enable input (active LOW)
supply voltage
ground supply voltage
select input
independent input or output
common output or input
supply voltage
Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7 13, 14, 15, 12, 1, 5, 2, 4
HEF4051B_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 12 July 2012
5 of 21
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