HEF4021B
NXP Semiconductors
8-bit static shift register
Table 8.
Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C.
Symbol
Parameter
VDD
5 V
Typical formula for PD (W)
PD = 900 fi + (fo CL) VDD
where:
2
PD
dynamic power
dissipation
fi = input frequency in MHz,
2
fo = output frequency in MHz,
CL = output load capacitance in pF,
10 V
15 V
PD = 4300 fi + (fo CL) VDD
2
PD = 12000 fi + (fo CL) VDD
VDD = supply voltage in V,
(fo CL) = sum of the outputs.
11. Waveforms
V
DD
CP or PL INPUT
V
M
V
SS
t
t
PLH
PHL
V
OH
V
Y
Qn OUTPUT
V
M
V
X
V
OL
001aaj060
t
t
t
t
Fig 4. Waveforms showing propagation delays for CP and PL inputs to Qn output and Qn transition times
1 / f
clk(max)
V
DD
CP INPUT
V
M
V
SS
t
t
h
su
t
W
V
DD
DS INPUT
V
M
V
SS
001aae611
Fig 5. Waveforms showing minimum clock pulse width, set-up time, and hold time for CP and DS.
HEF4021B
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 9 — 30 August 2013
7 of 16
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