HEF4021B
NXP Semiconductors
8-bit static shift register
Table 3.
Function table[1] …continued
Number of clock Inputs
Outputs
Q5
transitions
CP
DS
X
PL
L
Q6
Q7
8
data 3
data 2
data 1
X
L
no change
no change
D6
no change
D7
Parallel operation
X
X
H
D5
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care;
= LOW to HIGH clock transition; = HIGH to LOW clock transition;
data n = data (HIGH or LOW) on the DS input at the nth CP transition.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VDD
IIK
Parameter
Conditions
Min
0.5
-
Max
+18
10
Unit
V
supply voltage
input clamping current
input voltage
VI < 0.5 V or VI > VDD + 0.5 V
VO < 0.5 V or VO > VDD + 0.5 V
mA
VI
0.5
-
VDD + 0.5
10
V
IOK
output clamping current
input/output current
supply current
mA
mA
mA
C
C
II/O
-
10
IDD
-
50
Tstg
Tamb
Ptot
storage temperature
ambient temperature
total power dissipation
65
40
+150
+125
Tamb 40 C to +125 C
DIP16 package
[1]
[2]
-
-
-
750
500
100
mW
mW
mW
SO16 and TSSOP16 package
per output
P
power dissipation
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
For TSSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C.
8. Recommended operating conditions
Table 5.
Symbol
VDD
Recommended operating conditions
Parameter
Conditions
Min
Typ
Max
15
Unit
V
supply voltage
3
-
-
-
-
-
-
VI
input voltage
0
VDD
+125
3.75
0.5
V
Tamb
ambient temperature
input transition rise and fall rate
in free air
40
C
t/V
VDD = 5 V
VDD = 10 V
VDD = 15 V
-
-
-
s/V
s/V
s/V
0.08
HEF4021B
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 9 — 30 August 2013
4 of 16
NXP [ NXP ]
