HEF4021B
NXP Semiconductors
8-bit static shift register
Table 7.
Dynamic characteristics …continued
VSS = 0 V; Tamb = 25 C; for test circuit see Figure 7; unless otherwise specified.
Symbol Parameter
Conditions
VDD
5 V
Extrapolation formula
88 ns + (0.55 ns/pF)CL
39 ns + (0.23 ns/pF)CL
32 ns + (0.16 ns/pF)CL
78 ns + (0.55 ns/pF)CL
39 ns + (0.23 ns/pF)CL
32 ns + (0.16 ns/pF)CL
10 ns + (1.00 ns/pF)CL
9 ns + (0.42 ns/pF)CL
6 ns + (0.28 ns/pF)CL
Min Typ Max Unit
[1]
tPLH
LOW to HIGH
CP to Qn
see Figure 4
-
-
-
-
-
-
-
-
-
115
50
230 ns
100 ns
propagation delay
10 V
15 V
5 V
40
80
ns
PL to Qn
see Figure 4
105 210 ns
10 V
15 V
5 V
50
40
60
30
20
100 ns
80 ns
120 ns
[1]
tt
transition time
set-up time
Qn; see Figure 4
10 V
15 V
5 V
60
40
-
ns
ns
tsu
DS to CP;
see Figure 5
+25 15
+25 10
+15 5
ns
10 V
15 V
5 V
-
ns
-
ns
Dn to PL;
see Figure 6
50
30
20
40
20
15
25
10
5
-
ns
10 V
15 V
5 V
-
ns
-
ns
th
hold time
DS to CP;
see Figure 5
20
10
8
-
ns
10 V
15 V
5 V
-
ns
-
ns
Dn to PL;
+15 10
-
ns
see Figure 6
10 V
15 V
5 V
15
15
70
30
24
70
30
24
50
40
35
6
0
-
ns
0
-
ns
tW
pulse width
CP = LOW;
minimum width;
see Figure 5
35
15
12
35
15
12
10
5
-
ns
10 V
15 V
5 V
-
ns
-
ns
PL = HIGH;
minimum width;
see Figure 6
-
ns
10 V
15 V
5 V
-
ns
-
ns
trec
recovery time
PL input;
see Figure 6
-
ns
10 V
15 V
5 V
-
ns
5
-
ns
fclk(max)
maximum clock
frequency
CP input;
see Figure 5
13
30
40
-
MHz
MHz
MHz
10 V
15 V
15
20
-
-
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
HEF4021B
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 9 — 30 August 2013
6 of 16
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