NXP Semiconductors
HEF4021B
8-bit static shift register
Table 3.
Function table
[1]
…continued
Outputs
DS
X
X
X
PL
L
L
H
Q5
data 3
no change
D5
Q6
data 2
no change
D6
Q7
data 1
no change
D7
Number of clock Inputs
transitions
CP
8
Parallel operation
X
[1]
↑
↓
H = HIGH voltage level; L = LOW voltage level; X = don’t care;
↑
= LOW to HIGH clock transition;
↓
= HIGH to LOW clock transition;
data n = data (HIGH or LOW) on the DS input at the n
th
↑
CP transition.
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
V
DD
I
IK
V
I
I
OK
I
I/O
I
DD
T
stg
T
amb
P
tot
Parameter
supply voltage
input clamping current
input voltage
output clamping current
input/output current
supply current
storage temperature
ambient temperature
total power dissipation
T
amb
−40 °C
to +125
°C
DIP16 package
SO16 package
P
[1]
[2]
Conditions
V
I
<
−0.5
V or V
I
> V
DD
+ 0.5 V
V
O
<
−0.5
V or V
O
> V
DD
+ 0.5 V
Min
−0.5
-
−0.5
-
-
-
−65
−40
-
-
-
Max
+18
±10
V
DD
+ 0.5
±10
±10
50
+150
+125
750
500
100
Unit
V
mA
V
mA
mA
mA
°C
°C
mW
mW
mW
power dissipation
per output
For DIP16 package: P
tot
derates linearly with 12 mW/K above 70
°C.
For SO16 package: P
tot
derates linearly with 8 mW/K above 70
°C.
9. Recommended operating conditions
Table 5.
Symbol
V
DD
V
I
T
amb
∆t/∆V
Recommended operating conditions
Parameter
supply voltage
input voltage
ambient temperature
input transition rise and fall rate
in free air
V
DD
= 5 V
V
DD
= 10 V
V
DD
= 15 V
Conditions
Min
3
0
−40
-
-
-
Typ
-
-
-
-
-
-
Max
15
V
DD
+125
3.75
0.5
0.08
Unit
V
V
°C
µs/V
µs/V
µs/V
HEF4021B_6
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 06 — 27 November 2009
4 of 14
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