HEF40106B-Q100
NXP Semiconductors
Hex inverting Schmitt trigger
12. Waveforms
t
t
f
r
V
I
90 %
input
V
M
10 %
0 V
t
t
PLH
PHL
V
OH
90 %
output
V
M
10 %
V
OL
t
t
THL
TLH
001aag197
Measurement points are given in Table 9.
Logic levels: VOL and VOH are typical output voltage levels that occur with the output load.
tr, tf = input rise and fall times.
Fig 4. Propagation delay and output transition time
Table 9.
Measurement points
Supply voltage
VDD
Input
VM
Output
VM
5 V to 15 V
0.5VDD
0.5VDD
V
DD
V
V
O
I
G
DUT
C
L
R
T
001aag182
Test data given in Table 10.
Definitions for test circuit:
DUT = Device Under Test.
CL = load capacitance including jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig 5. Test circuit
Table 10. Test data
Supply voltage
VDD
Input
Load
CL
VI
tr, tf
5 V to 15 V
VSS or VDD
20 ns
50 pF
HEF40106B_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
6 of 15
NXP [ NXP ]
