NXP Semiconductors
HEF40106B-Q100
Hex inverting Schmitt trigger
12. Waveforms
t
r
V
I
input
0V
t
f
90 %
V
M
10 %
t
PHL
t
PLH
V
OH
output
V
OL
90 %
V
M
10 %
t
THL
t
TLH
001aag197
Measurement points are given in
Logic levels: V
OL
and V
OH
are typical output voltage levels that occur with the output load.
t
r
, t
f
= input rise and fall times.
Fig 4.
Table 9.
V
DD
Propagation delay and output transition time
Measurement points
Input
V
M
0.5V
DD
Output
V
M
0.5V
DD
Supply voltage
5 V to 15 V
V
DD
V
I
G
RT
V
O
DUT
CL
001aag182
Test data given in
Definitions for test circuit:
DUT = Device Under Test.
C
L
= load capacitance including jig and probe capacitance.
R
T
= termination resistance should be equal to the output impedance Z
o
of the pulse generator.
Fig 5.
Table 10.
V
DD
Test circuit
Test data
Input
V
I
V
SS
or V
DD
t
r
, t
f
20 ns
Load
C
L
50 pF
Supply voltage
5 V to 15 V
HEF40106B_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 7 August 2012
6 of 15
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