NXP Semiconductors
74LVC74A
Dual D-type flip-flop with set and reset; positive-edge trigger
5.2 Pin description
Table 2.
Symbol
1RD
1D
1CP
1SD
1Q
1Q
GND
2Q
2Q
2SD
2CP
2D
2RD
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Description
asynchronous reset-direct input (active LOW)
data input
clock input (LOW-to-HIGH, edge-triggered)
asynchronous set-direct input (active LOW)
true output
complement output
ground (0 V)
complement output
true output
asynchronous set-direct input (active LOW)
clock input (LOW-to-HIGH, edge-triggered)
data input
asynchronous reset-direct input (active LOW)
supply voltage
6. Functional description
Table 3.
Input
nSD
L
H
L
[1]
Function table
Output
nRD
H
L
L
nCP
X
X
X
nD
X
X
X
nQ
H
L
H
nQ
L
H
H
H = HIGH voltage level
L = LOW voltage level
X = don’t care
Table 4.
Input
nSD
H
H
[1]
Function table
Output
nRD
H
H
nCP
nD
L
H
nQ
n+1
L
H
nQ
n+1
H
L
H = HIGH voltage level
L = LOW voltage level
= LOW-to-HIGH transition
Q
n+1
= state after the next LOW-to-HIGH CP transition
X = don’t care
74LVC74A
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 7 — 20 November 2012
4 of 19
PHILIPS [ NXP SEMICONDUCTORS ]
