Philips Semiconductors
Product specification
Quad 2-input NAND gate
74LV00
PIN CONFIGURATION
LOGIC SYMBOL
1A
1B
1
2
1A
1B
1Y
2A
2B
1
2
3
4
5
14
V
1Y
CC
3
13 4B
12 4A
11 4Y
10 3B
2A
2B
4
5
2Y
3Y
4Y
6
8
3A
3B
9
10
4A
4B
2Y
6
7
9
8
3A
3Y
12
13
11
GND
SY00035
SY00034
LOGIC SYMBOL (IEEE/IEC)
LOGIC DIAGRAM (ONE GATE)
&
1
3
A
2
Y
&
&
&
4
5
6
B
SV00379
9
8
10
12
13
11
SV00378
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
MIN
1.0
0
TYP.
3.3
–
MAX
UNIT
V
CC
DC supply voltage
See Note 1
5.5
V
V
V
V
I
Input voltage
V
CC
V
CC
V
O
Output voltage
0
–
See DC and AC
characteristics
–40
–40
+85
+125
T
Operating ambient temperature range in free air
Input rise and fall times
°C
amb
V
V
V
V
= 1.0V to 2.0V
= 2.0V to 2.7V
= 2.7V to 3.6V
= 3.6V to 5.5V
–
–
–
–
–
–
–
–
500
200
100
50
CC
CC
CC
CC
t , t
r
ns/V
f
NOTE:
1. The LV is guaranteed to function down to V = 1.0V (input levels GND or V ); DC characteristics are guaranteed from V = 1.2V to V = 5.5V.
CC
CC
CC
CC
3
1998 Apr 20
NXP [ NXP ]
