Philips Semiconductors
Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
Family 74HCT
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF.
TEST CONDITIONS
SYMBOL
PARAMETER
WAVEFORMS
T
amb
=
−40
to +85
°C
t
PHL
/t
PLH
propagation
delay nCP to nQ, nQ
propagation
delay nSD to nQ, nQ
propagation
delay nRD to nQ, nQ
t
THL
/t
TLH
t
W
output transition time
see Fig.7
see Fig.8
see Fig.8
see Fig.7
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
−
−
−
−
23
20
8
15
+3
22
V
CC
(V)
MIN.
74HC74; 74HCT74
TYP.
MAX.
UNIT
18
23
24
7
9
9
1
5
−3
54
44
50
50
19
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
clock pulse width HIGH see Fig.7
or LOW
set or reset pulse width see Fig.8
LOW
t
rem
t
su
t
h
f
max
removal time set or
reset
set-up time nD to nCP
hold time nCP to nD
maximum clock pulse
frequency
see Fig.8
see Fig.7
see Fig.7
see Fig.7
T
amb
=
−40
to +125
°C
t
PHL
/t
PLH
propagation
delay nCP to nQ, nQ
propagation
delay nSD to nQ, nQ
propagation
delay nRD to nQ, nQ
t
THL
/t
TLH
t
W
output transition time
see Fig.7
see Fig.8
see Fig.8
see Fig.7
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
−
−
−
−
27
24
9
18
3
18
−
−
−
−
−
−
−
−
−
−
53
60
60
22
−
−
−
−
−
−
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
clock pulse width HIGH see Fig.7
or LOW
set or reset pulse width see Fig.8
LOW
t
rem
t
su
t
h
f
max
removal time set or
reset
set-up time nD to nCP
hold time nCP to nD
maximum clock pulse
frequency
see Fig.8
see Fig.7
see Fig.7
see Fig.7
2003 Jul 10
12
PHILIPS [ NXP SEMICONDUCTORS ]
