Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
AC WAVEFORMS
74HC/HCT109
The shaded areas indicate when the
input is permitted to change for
predictable output performance.
Fig.6
Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nJ,
nK to nCP set-up, the nCP to nJ, nK hold times, the output transition times and the maximum clock pulse
frequency.
handbook, full pagewidth
nCP INPUT
VM
(1)
trem
nSD INPUT
VM
(1)
tW
trem
tW
nRD INPUT
VM
(1)
tPLH
tPHL
nQ OUTPUT
VM
(1)
tPHL
tPLH
nQ OUTPUT
VM
(1)
MBK216
(1) HC: V
M
= 50%; V
I
= GND to V
CC
.
HCT: V
M
= 1.3 V; V
I
= GND to 3 V.
Fig.7
Waveforms showing the set (nS
D
) and reset (nR
D
) input to output (nQ, nQ) propagation delays, the set
and reset pulse widths and the nR
D
, nS
D
to nCP removal time.
1997 Nov 25
7
PHILIPS [ NXP SEMICONDUCTORS ]
