Philips Semiconductors
Product specification
Dual JK flip-flop with set and reset;
positive-edge trigger
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”.
Output capability: standard
I
CC
category: flip-flops
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r
= t
f
= 6 ns; C
L
= 50 pF
T
amb
(°C)
SYMBOL
PARAMETER
min.
t
PHL
/ t
PLH
propagation delay
nCP to nQ, nQ
propagation delay
nS
D
to nQ
propagation delay
nS
D
to nQ
propagation delay
nR
D
to nQ
propagation delay
nR
D
to nQ
output transition
time
80
16
14
80
set or reset pulse
16
width HIGH or LOW
14
70
removal time
14
nS
D
, nR
D
to nCP
12
clock pulse width
HIGH or LOW
set-up time
nJ, nK to nCP
hold time
nJ, nK to nCP
maximum clock
pulse frequency
70
14
12
5
5
5
6.0
30
35
74HC
+25
typ.
50
18
14
30
11
9
41
15
12
41
15
12
39
14
11
19
7
6
19
7
6
14
5
4
19
7
6
17
6
5
0
0
0
22
68
81
max.
175
35
30
120
24
20
155
31
26
185
37
31
170
34
29
75
15
13
100
20
17
100
20
17
90
18
15
90
18
15
5
5
5
5.0
24
28
5
−40
to
+85
min.
max.
220
44
37
150
30
26
195
39
33
230
46
39
215
43
37
95
19
16
120
24
20
120
24
20
105
21
18
105
21
18
5
5
5
4.0
20
24
−40
to
+125
min.
max.
265
53
45
180
36
31
235
47
40
280
56
48
255
51
43
110
22
19
ns
UNIT
74HC/HCT109
TEST CONDITIONS
V
CC
WAVEFORMS
(V)
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
Fig.6
t
PLH
ns
Fig.7
t
PHL
ns
Fig.7
t
PHL
ns
Fig.7
t
PLH
ns
Fig.7
t
THL
/ t
TLH
ns
Fig.6
t
W
ns
Fig.6
t
W
ns
Fig.7
t
rem
ns
Fig.7
t
su
ns
Fig.6
t
h
ns
Fig.6
f
max
MHz
Fig.6
1997 Nov 25
PHILIPS [ NXP SEMICONDUCTORS ]
