NXP Semiconductors
74HC573-Q100; 74HCT573-Q100
Octal D-type transparent latch; 3-state
V
I
OE input
GND
t
PLZ
V
CC
output
LOW-to-OFF
OFF-to-LOW
V
OL
t
PHZ
V
OH
output
HIGH-to-OFF
OFF-to-HIGH
GND
outputs
enabled
90%
V
M
V
M
10%
t
PZH
t
PZL
V
M
outputs
disabled
outputs
enabled
001aae307
Measurement points are given in
V
OL
and V
OH
are typical voltage output levels that occur with the output load.
Fig 9.
Enable and disable times
LE input
V
M
t
su
t
h
t
su
t
h
Dn input
V
M
001aae084
Measurement points are given in
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 10. Set-up and hold times for data input (Dn) to latch input (LE)
Table 8.
Type
74HC573-Q100
74HCT573-Q100
Measurement points
Input
V
M
0.5V
CC
1.3 V
Output
V
M
0.5V
CC
1.3 V
74HC_HCT573_Q100
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© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 5 March 2013
11 of 20
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