74HC373-Q100; 74HCT373-Q100
NXP Semiconductors
Octal D-type transparent latch; 3-state
6. Functional description
6.1 Function table
Table 3.
Function table[1]
Operating mode
Control
Input
Internal latches
Output
OE
LE
Dn
L
Qn
L
Enable and read register
(transparent mode)
L
H
L
H
l
H
L
H
L
Latch and read register
L
L
h
H
X
H
Z
Latch register and disable
outputs
H
X
X
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;
X = don’t care;
Z = high-impedance OFF-state.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
VCC
IIK
Parameter
Conditions
Min
Max
+7
Unit
V
supply voltage
0.5
input clamping current
output clamping current
output current
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to (VCC + 0.5 V)
-
20
20
35
+70
70
+150
500
500
500
mA
mA
mA
mA
mA
C
IOK
-
IO
-
ICC
supply current
-
IGND
Tstg
Ptot
ground current
-
storage temperature
total power dissipation
65
[1]
[2]
[3]
SO20 package
-
mW
mW
mW
TSSOP20 package
DHVQFN20 package
-
[1] For SO20: Ptot derates linearly with 8 mW/K above 70 C.
[2] For TSSOP20 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
[3] For DHVQFN20 package: Ptot derates linearly with 4.5 mW/K above 60 C.
74HC_HCT373_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 10 August 2012
5 of 24
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