74HC373-Q100; 74HCT373-Q100
NXP Semiconductors
Octal D-type transparent latch; 3-state
5. Pinning information
5.1 Pinning
ꢀꢁꢂꢃꢄꢀꢄꢅꢆꢇꢈꢈ
ꢀꢁꢂꢃꢉꢄꢀꢄꢅꢆꢇꢈꢈ
ꢀꢁꢂꢃꢄꢀꢄꢅꢆꢇꢈꢈ
ꢀꢁꢂꢃꢉꢄꢀꢄꢅꢆꢇꢈꢈ
ꢕꢖꢗꢘꢙꢚꢛꢜꢝꢊ
ꢙꢚ ꢖ!ꢝꢛꢗꢖꢛ
ꢊ
ꢋ
ꢋꢏ
ꢊꢎ
ꢊꢍ
ꢊꢃ
ꢊꢅ
ꢊꢆ
ꢊꢇ
ꢊꢌ
ꢊꢋ
ꢊꢊ
ꢐꢉ
ꢂꢏ
ꢀ
ꢁꢁ
ꢂꢃ
ꢄꢃ
ꢄꢅ
ꢂꢅ
ꢂꢆ
ꢄꢆ
ꢄꢇ
ꢂꢇ
ꢈꢉ
ꢋ
ꢌ
ꢇ
ꢆ
ꢅ
ꢃ
ꢍ
ꢎ
ꢊꢎ
ꢊꢍ
ꢊꢃ
ꢂꢏ
ꢄꢏ
ꢄꢊ
ꢂꢊ
ꢂꢋ
ꢄꢋ
ꢄꢌ
ꢂꢌ
ꢂꢃ
ꢄꢃ
ꢄꢅ
ꢌ
ꢄꢏ
ꢇ
ꢄꢊ
ꢆ
ꢊꢅ ꢂꢅ
ꢂꢊ
ꢊꢆ
ꢊꢇ
ꢊꢌ
ꢊꢋ
ꢂꢆ
ꢄꢆ
ꢄꢇ
ꢂꢇ
ꢅ
ꢂꢋ
ꢃ
ꢄꢋ
ꢓꢊꢔ
ꢑꢒꢄ
ꢍ
ꢄꢌ
ꢎ
ꢂꢌ
ꢊꢏ
ꢑꢒꢄ
ꢀꢀꢀꢁꢂꢂꢃꢄꢅꢇ
"ꢗꢛꢚ#$ꢛꢗꢖꢚꢕꢝꢕ%$ꢝ&ꢙꢖ'
ꢀꢀꢀꢁꢂꢂꢃꢄꢅꢆ
(1) The die substrate is attached to this pad using
conductive die attach material. It cannot be used as
supply pin or input.
Fig 6. Pin configuration SO20 and TSSOP20
Fig 7. Pin configuration DHVQFN20
5.2 Pin description
Table 2.
Symbol
OE
Pin description
Pin
Description
1
3-state output enable input (active LOW)
3-state latch output
data input
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
2, 5, 6, 9, 12, 15, 16, 19
D0, D1, D2, D3, D4, D5, D6, D7
3, 4, 7, 8, 13, 14, 17, 18
GND
LE
10
11
20
ground (0 V)
latch enable input (active HIGH)
supply voltage
VCC
74HC_HCT373_Q100
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© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 10 August 2012
4 of 24
NXP [ NXP ]
