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74HC165BQ-G 参数 Datasheet PDF下载

74HC165BQ-G图片预览
型号: 74HC165BQ-G
PDF下载: 下载PDF文件 查看货源
内容描述: [IC,SHIFT REGISTER,HC-CMOS,LLCC,16PIN,PLASTIC]
分类和应用: 移位寄存器
文件页数/大小: 10 页 / 77 K
品牌: PHILIPS [ NXP SEMICONDUCTORS ]
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Philips Semiconductors
Product specification
8-bit parallel-in/serial-out shift register
FEATURES
Asynchronous 8-bit parallel load
Synchronous serial input
Output capability: standard
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT165 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT165 are 8-bit parallel-load or serial-in shift
registers with complementary serial outputs (Q
7
and
Q
7
) available from the last stage. When the parallel load
(PL) input is LOW, parallel data from the D
0
to
D
7
inputs are loaded into the register asynchronously.
74HC/HCT165
When PL is HIGH, data enters the register serially at the
D
s
input and shifts one place to the right
(Q
0
Q
1
Q
2
, etc.) with each positive-going clock
transition. This feature allows parallel-to-serial converter
expansion by tying the Q
7
output to the D
S
input of the
succeeding stage.
The clock input is a gated-OR structure which allows one
input to be used as an active LOW clock enable (CE) input.
The pin assignment for the CP and CE inputs is arbitrary
and can be reversed for layout convenience. The
LOW-to-HIGH transition of input CE should only take
place while CP HIGH for predictable operation. Either the
CP or the CE should be HIGH before the
LOW-to-HIGH transition of PL to prevent shifting the data
when PL is activated.
APPLICATIONS
Parallel-to-serial data conversion
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
TYPICAL
SYMBOL
t
PHL
/ t
PLH
PARAMETER
propagation delay
CP to Q
7,
Q
7
PL to Q
7,
Q
7
D
7
to Q
7,
Q
7
maximum clock frequency
input capacitance
power dissipation capacitance per
package
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
16
15
11
56
3.5
35
14
17
11
48
3.5
35
ns
ns
ns
MHz
pF
pF
HCT
UNIT
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
December 1990
2