NXP Semiconductors
74HC165-Q100; 74HCT165-Q100
8-bit parallel-in/serial out shift register
CP
CE
DS
PL
D0
D1
D2
D3
D4
D5
D6
D7
Q7
Q7
inhibit
load
serial shift
mna993
Fig 6.
Timing diagram
8. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
Symbol
V
CC
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
Parameter
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
<
0.5
V or V
I
> V
CC
+ 0.5 V
V
O
<
0.5
V or V
O
> V
CC
+ 0.5 V
0.5
V < V
O
< V
CC
+ 0.5 V
Min
0.5
-
-
-
-
50
65
Max
+7
20
20
25
50
-
+150
500
Unit
V
mA
mA
mA
mA
mA
C
mW
T
amb
=
40 C
to +125
C
-
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
For SO16 package: P
tot
derates linearly with 8 mW/K above 70
C.
For TSSOP16 package: P
tot
derates linearly with 5.5 mW/K above 60
C.
For DHVQFN16 package: P
tot
derates linearly with 4.5 mW/K above 60
C.
74HC_HCT165_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 1 — 17 July 2012
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