Philips Semiconductors
Product specification
Presettable synchronous 4-bit binary
counter; asynchronous reset
74HC/HCT161
input (PE) disables the counting action and causes the
data at the data inputs (D0 to D3) to be loaded into the
counter on the positive-going edge of the clock (providing
that the set-up and hold time requirements for PE are met).
Preset takes place regardless of the levels at count enable
inputs (CEP and CET).
FEATURES
• Synchronous counting and loading
• Two count enable inputs for n-bit cascading
• Positive-edge triggered clock
• Asynchronous reset
A LOW level at the master reset input (MR) sets all four
outputs of the flip-flops (Q0 to Q3) to LOW level regardless
of the levels at CP, PE, CET and CEP inputs (thus
providing an asynchronous clear function).
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The look-ahead carry simplifies serial cascading of the
counters. Both count enable inputs (CEP and CET) must
be HIGH to count. The CET input is fed forward to enable
the terminal count output (TC). The TC output thus
enabled will produce a HIGH output pulse of a duration
approximately equal to a HIGH level output of Q0. This
pulse can be used to enable the next cascaded stage.
The 74HC/HCT161 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT161 are synchronous presettable binary
counters which feature an internal look-ahead carry and
can be used for high-speed counting.
Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the
clock (CP).
The maximum clock frequency for the cascaded counters
is determined by the CP to TC propagation delay and CEP
to CP set-up time, according to the following formula:
1
The outputs (Q0 to Q3) of the counters may be preset to a
HIGH or LOW level. A LOW level at the parallel enable
--------------------------------------------------------------------------------------------------
fmax
=
tP(max) (CP to TC) + tSU (CEP to CP)
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns
Notes
TYPICAL
SYMBOL PARAMETER
CONDITIONS
UNIT
1. CPD is used to determine the
dynamic power dissipation
(PD in µW):
HC HCT
t
PHL/ tPLH propagation delay
CP to Qn
CL = 15 pF;
VCC = 5 V
19
20
24
25
26
14
ns
ns
ns
ns
ns
PD = CPD × VCC2 × fi +
∑ (CL × VCC2 × fo)
where:
CP to TC
MR to Qn
MR to TC
CET to TC
21
20
20
10
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of
fmax
CI
maximum clock frequency
input capacitance
44
45
3.5
35
MHz
pF
3.5
outputs
CPD
power dissipation
notes 1 and 2 33
pF
CL = output load capacitance in
pF
capacitance per package
VCC = supply voltage in V
2. For HC the condition is
VI = GND to VCC
For HCT the condition is
VI = GND to VCC − 1.5 V
December 1990
2
NXP [ NXP ]
