Philips Semiconductors
Product specification
Quad 2-input NAND gate
FEATURES
•
Level shift capability
•
Output capability: standard (open drain)
•
I
CC
category: SSI
GENERAL DESCRIPTION
The 74HC/HCT03 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT03
The 74HC/HCT03 provide the 2-input NAND function.
The 74HC/HCT03 have open-drain N-transistor outputs,
which are not clamped by a diode connected to V
CC
. In
the OFF-state, i.e. when one input is LOW, the output
may be pulled to any voltage between GND and V
Omax
.
This allows the device to be used as a LOW-to-HIGH or
HIGH-to-LOW level shifter. For digital operation and
OR-tied output applications, these devices must have a
pull-up resistor to establish a logic HIGH level.
TYPICAL
SYMBOL
t
PZL
/ t
PLZ
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) +
∑
(V
O2
/R
L
)
×
duty factor LOW, where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
V
O
= output voltage in V
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
R
L
= pull-up resistor in MΩ
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
∑
(V
O2
/R
L
) = sum of outputs
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
3. The given value of C
PD
is obtained with:
C
L
= 0 pF and R
L
=
∞
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
PARAMETER
propagation delay
input capacitance
power dissipation capacitance per gate
notes 1, 2 and 3
CONDITIONS
HC
C
L
= 15 pF; R
L
= 1 kΩ; V
CC
= 5 V
8
3.5
4.0
HCT
10
3.5
4.0
ns
pF
pF
UNIT
December 1990
2
PHILIPS [ NXP SEMICONDUCTORS ]
