PE3291
Product Specification
Figure 2. Pin Configurations (Top View)
N/C
V
DD
CP1
GND
f
in
1
Dec1
V
DD
1
f
r
GND
1
2
3
4
5
6
7
8
9
20
V
DD
19
V
DD
18
CP2
17
GND
16
f
in
2
15
Dec2
14
V
DD
2
13
LE
12
Data
11
Clock
Figure 3. Package Type
20-lead TSSOP
f
o
LD
10
Table 1. Pin Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Name
N/C
V
DD
CP1
GND
f
in
1
Dec1
V
DD1
f
r
GND
f
o
LD
Clock
Data
LE
V
DD2
Dec2
F
in
2
GND
CP2
V
DD
V
DD
Type
No connect.
(Note 1)
Output
Description
Power supply voltage input. Input may range from 2.7 V to 3.3 V. A bypass capacitor should be placed
as close as possible to this pin and be connected directly to the ground plane.
Internal charge-pump output from PLL1 for connection to a loop filter for driving the input of an external
VCO.
Ground.
Input
Prescaler input from the PLL1 (RF) VCO. Maximum frequency is 1.2 GHz.
Power supply decoupling pin for PLL1. A capacitor should be placed as close as possible to this pin and
be connected directly to the ground plane.
PLL1 prescaler power supply (FlexiPower 1).
Input
Reference frequency input.
Ground.
Output
Input
Input
Input
Output
Output
Input
Multiplexed output of the PLL1 and PLL2 main counters or reference counters, Lock Detect signals, and
data out of the shift register. CMOS output (see Table 11, f
o
LD Programming Truth Table).
CMOS clock input. Serial data for the various counters is clocked in on the rising edge into the 21-bit shift
register.
Binary serial data input. CMOS input data entered MSB first. The two LSBs are the control bits.
Load Enable CMOS input. When LE is high, data word stored in the 21-bit serial shift register is loaded
into one of the four appropriate latches (as assigned by the control bits).
PLL2 prescaler power supply (FlexiPower 2).
Power supply decoupling pin for PLL2. A capacitor should be placed as close as possible to this pin and
be connected directly to the ground plane.
Prescaler input from the PLL2 (IF) VCO. Maximum frequency is 550 MHz.
Ground.
Output
(Note 1)
(Note 1)
Internal charge-pump output for PLL2. For connection to a loop filter for driving the input of an external
VCO.
Same as pin 2.
Same as pin 2.
Note 1:
V
DD
pins 2, 19, and 20 are connected by diodes and must be supplied with the same voltage level.
©2005 Peregrine Semiconductor Corp. All rights reserved.
Page 2 of 15
Document No. 70-0009-04
│
UltraCMOS™ RFIC Solutions
PEREGRINE [ PEREGRINE SEMICONDUCTOR CORP. ]
