PE3291
Product Specification
Functional Description
The Functional Block Diagram in Figure 7 shows a
21-bit serial control register, a multiplexed output,
and PLL sections PLL1 and PLL2. Each PLL
contains a fractional-N main counter chain, a
reference counter, a phase detector, and an
internal charge pump with on-chip fractional spur
compensation. Each fractional-N main counter
chain includes an internal dual modulus prescaler,
supporting counters, and a fractional accumulator.
Serial input data is clocked on the rising edge of
Clock, MSB first. The last two bits are the address
bits that determine the register address. Data is
transferred into the counters as shown in Table 8,
PE3291 Register Set. If the f
o
LD pin is configured
as data out, then the contents of shift register bit
S
20
are clocked on the falling edge of Clock onto
the f
o
LD pin. This feature allows the PE3291 and
compatible devices to be connected in a daisy-
chain configuration.
The PLL1 (RF) VCO frequency f
in
1 is related to
Figure 7. Functional Block Diagram
A
1
5
the reference frequency f
r
by the following
equation:
f
in
1 = [(32 x M
1
) + A
1
+ (F
1
/32)] x (f
r
/R
1
)
(1) Note that A
1
must be less than M
1
. Also, f
in
1
must be greater than or equal to 1024 x (f
r
/R
1
) to
obtain contiguous channels.
The PLL2 (IF) VCO frequency f
in
2 is related to the
reference frequency f
r
by the following equation:
f
in
2 = [(16 x M2) + A
2
+ (F
2
/32)] x (f
r
/R
2
)
(2) Note that A
2
must be less than M
2
. Also, f
in
2
must be greater than or equal to 256 x (f
r
/R
2
) to
obtain contiguous channels.
F
1
sets PLL1 fractionality. If F
1
is an even number,
the PE3291 automatically reduces the fraction.
For example, if F
1
= 12, then the fraction 12/32 is
automatically reduced to 3/8. In this way,
fractional denominators of 2, 4, 8, 16 and 32 are
available. F
2
sets the fractionality for PLL2 in the
same manner.
A
1
Counter
0<A
1
<31
P
1
P
2
M
1
9
Prescaler
Control Logic
F
1
5
f
in
1
32/33
Prescaler
M
1
Counter
3<M
1
<511
F
1
Counter
0<F
1
<31
Fractional Spur
Compensation
f
r
Ref.
Amp.
9-bit Reference
Divider
R
1
9
Phase
Detector
C
11
Charge
Pump
C
12
C
22
C
22
C
22
C
22
CP1
Clock
Data
LE
21-bit Serial Control
Interface
R
2
9
Multiplexer
C
21
C
22
f
o
LD
9-bit Reference
Divider
Phase
Detector
Charge
Pump
CP2
f
in
2
16/17
Prescaler
M
2
Counter
3<M
2
<511
M
2
9
F
2
Counter
0<F
2
<31
F
2
5
Fractional Spur
Compensation
P
1
P
2
A
2
Counter
0<A
2
<15
A
2
4
Prescaler
Control Logic
Document No. 70-0009-04
│
www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
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