PE3291
Product Specification
Programmable Divide Values
(R1, R2, F1, F2, A1, A2, M1, M2)
Table 8. PE3291 Counter Programming Example
Divide Value
MSB
S
11
A
14
0
1
2
-
31
0
0
0
-
1
S
10
A
13
0
0
0
-
1
S
9
A
12
0
0
0
-
1
S
8
A
11
0
0
1
-
1
LSB
S
7
A
10
0
1
0
-
1
Address
S
1
1
1
1
1
1
1
S
0
1
1
1
1
1
1
Data is clocked into the 21-bit shift register, MSB
first. When LE is asserted HIGH, data is latched
into the registers addressed by the last two bits
shifted into the 21-bit register, according to Table
7. For example, to program the PLL1 (RF)
swallow counter, A1, the last two bits shifted into
the register (S0, S1) would be (1,1). The 5-bit A1
counter would then be programmed according to
Table 8. For normal operation, S16 of address
(0,0) (the Test bit) must be programmed to 0 even
if PLL2 (IF) is not used.
Program Modes
Several modes of operation can be programmed with bits C
10
- C
14
and C
20
- C
24
, including the phase detector
polarity, charge pump high impedance, output of the foLD pin and power-down modes. The PE3291 modes of
operation are shown on Table 9. The truth table for the foLD output is shown in Table 10.
Table 9. PE3291 Program Modes
S
15
C
24
See Table 10
C
23
See Table 10
S
14
C
22
S
13
C
21
(Note 2)
S
12
S
11
C
20
(Note 1)
0 = PLL2 on
1 = PLL2 off
C
10
(Note 1)
0 = PLL1 on
1 = PLL1 off
S
1
0
S
0
0
0 = PLL2 CP normal
1 = PLL2 CP High Z
0 = PLL2 Phase Detector inverted
1 = PLL2 Phase Detector normal
C
11
(Note 2)
0 = PLL1 Phase Detector inverted
1 = PLL1 Phase Detector normal
C
14
See Table 10
C
13
See Table 10
C
12
0 = PLL1 CP normal
1 = PLL1 CP High Z
1
0
Note 1:
The PLL1 power-down mode disables all of PLL1’s components except the R
1
counter and the reference frequency input buffer, with
CP1 (pin 3) and f
in
1 (pin 5) becoming high impedance. The power down of PLL2 has similar results with CP2 (pin 18) and f
in
2 (pin 16)
becoming high impedance. Power down of both PLL1 and PLL2 further disables counters R
1
and R
2
, the reference frequency input, and
the f
o
LD output, causing f
r
(pin 8) and f
o
LD (pin 10) to become high impedance. The Serial Control Interface remains active at all times.
The C
11
and C
21
bits should be set according to the voltage versus frequency slope of the VCO as shown in Figure 9. This relationship
presumes the use of a passive loop filter. If an inverting active loop filter is used the relationship is also inverted.
Note 2:
Figure 9. VCO Characteristics
VCO
Output
Frequency
(1) Positive slope VCO
•
•
•
•
When VCO1 (RF) slope is positive like (1), C
11
should be set HIGH.
When VCO1 (RF) slope is negative like (2), C
11
should be set LOW.
When VCO2 (IF) slope is positive like (1), C
21
should be set HIGH.
When VCO2 (IF) slope is negative like (2), C
21
should be set LOW.
(2) Negative slope VCO
VCO Input voltage
Document No. 70-0009-04
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©2005 Peregrine Semiconductor Corp. All rights reserved.
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