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3335-24 参数 Datasheet PDF下载

3335-24图片预览
型号: 3335-24
PDF下载: 下载PDF文件 查看货源
内容描述: 3000兆赫UltraCMOS⑩整数N分频PLL的低相位噪声应用 [3000 MHz UltraCMOS⑩ Integer-N PLL for Low Phase Noise Applications]
分类和应用:
文件页数/大小: 15 页 / 235 K
品牌: PSEMI [ Peregrine Semiconductor ]
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PE3335  
Product Specification  
Table 2. Absolute Maximum Ratings  
Table 4. ESD Ratings  
Symbol  
Parameter/Conditions Min Max Units  
Symbol  
Parameter/Conditions  
Level  
Units  
VDD  
VI  
Supply voltage  
-0.3  
-0.3  
4.0  
V
V
VESD  
ESD voltage (Human Body  
1000  
V
Voltage on any input  
VDD  
+
Note 1: Periodically sampled, not 100% tested. Tested per MIL-  
0.3  
STD-883, M3015 C2  
II  
DC into any input  
-10  
-10  
-65  
+10  
+10  
150  
mA  
mA  
°C  
IO  
DC into any output  
Electrostatic Discharge (ESD) Precautions  
Tstg  
Storage temperature range  
When handling this UltraCMOS™ device, observe  
the same precautions that you would use with  
other ESD-sensitive devices. Although this device  
contains circuitry to protect it from damage due to  
ESD, precautions should be taken to avoid  
exceeding the specified rating in Table 4.  
Table 3. Operating Ratings  
Symbol  
Parameter/Conditions Min Max Units  
VDD  
Supply voltage  
2.85  
-40  
3.15  
85  
V
Latch-Up Avoidance  
TA  
Operating ambient  
temperature range  
°C  
Unlike conventional CMOS devices, UltraCMOS™  
devices are immune to latch-up.  
Table 5. DC Characteristics: VDD = 3.0 V, -40° C < TA < 85° C, unless otherwise specified  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max  
Units  
IDD  
Operational supply current;  
Prescaler disabled  
VDD = 2.85 to 3.15 V  
10  
24  
mA  
mA  
Prescaler enabled  
31  
Digital Inputs: All except fr, R0, Fin, Fin  
VIH  
VIL  
IIH  
High level input voltage  
Low level input voltage  
High level input current  
Low level input current  
VDD = 2.85 to 3.15 V  
VDD = 2.85 to 3.15 V  
VIH = VDD = 3.15 V  
0.7 x VDD  
V
V
0.3 x VDD  
+70  
µA  
µA  
IIL  
VIL = 0, VDD = 3.15 V  
-1  
Reference Divider input: fr  
IIHR High level input current  
IILR Low level input current  
R0 Input (Pull-up Resistor): R0  
IIHRO High level input current  
IILRO Low level input current  
Counter output Dout  
VIH = VDD = 3.15 V  
+100  
+5  
µA  
µA  
VIL = 0, VDD = 3.15 V  
-100  
VIH = VDD = 3.15 V  
µA  
µA  
VIL = 0, VDD = 3.15 V  
-5  
VOLD  
VOHD  
Output voltage LOW  
Output voltage HIGH  
Iout = 6 mA  
Iout = -3 mA  
0.4  
V
V
VDD - 0.4  
VDD - 0.4  
Lock detect outputs: Cext, LD  
VOLC  
VOHC  
VOLLD  
Output voltage LOW, Cext  
Iout = 100 mA  
Iout = -100 mA  
Iout = 6 mA  
0.4  
0.4  
V
V
V
Output voltage HIGH, Cext  
Output voltage LOW, LD  
Charge Pump output: CP  
ICP - Source Drive current  
VCP = VDD / 2  
-2.6  
1.4  
-1  
-2  
2
-1.4  
2.6  
mA  
mA  
µA  
%
ICP – Sink  
Drive current  
VCP = VDD / 2  
ICPL  
Leakage current  
1.0 V < VCP < VDD – 1.0 V  
VCP = VDD / 2,  
TA = 25° C  
1
ICP – Source  
Sink vs. source mismatch  
15  
15  
vs. ICP Sink  
ICP vs. VCP  
Output current magnitude variation vs. voltage  
V < VCP < VDD – 1.0 V  
TA = 25° C  
%
Document No. 70-0049-02 www.psemi.com  
©2005 Peregrine Semiconductor Corp. All rights reserved.  
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