PE3335
Product Specification
Table 1. Pin Descriptions (continued)
Pin No.
Pin No.
Pin
Name
Interface
Mode
Type
Description
(44-lead
PLCC)
(48-lead
QFN)
Serial load enable input. While S_WR is “low”, Sdata can be serially clocked.
Primary register data are transferred to the secondary register on S_WR or
Hop_WR rising edge.
S_WR
Serial
Input
13
14
7
8
D4
M4
Parallel
Direct
Input
Input
Parallel data bus bit4
M Counter bit4
Sdata
D5
Serial
Input
Input
Input
Binary serial data input. Input data entered MSB first.
Parallel data bus bit5.
Parallel
Direct
M5
M Counter bit5.
Serial clock input. Sdata is clocked serially into the 20-bit primary register
(E_WR “low”) or the 8-bit enhancement register (E_WR “high”) on the rising
edge of Sclk.
Sclk
Serial
Input
15
16
9
D6
M6
Parallel
Direct
Input
Input
Parallel data bus bit6.
M Counter bit6.
Selects contents of primary register (FSELS=1) or secondary register
(FSELS=0) for programming of internal counters while in Serial Interface
Mode.
FSELS
Serial
Input
10
D7
Parallel
Direct
ALL
Input
Input
Parallel data bus bit7 (MSB).
Pre_en
GND
Prescaler enable, active “low”. When “high”, Fin bypasses the prescaler.
Ground.
17
18
11
12
Selects contents of primary register (FSELP=1) or secondary register
(FSELP=0) for programming of internal counters while in Parallel Interface
Mode.
FSELP
A0
Parallel
Input
Direct
Serial
Input
Input
A Counter bit0 (LSB).
Enhancement register write enable. While E_WR is “high”, Sdata can be
serially clocked into the enhancement register on the rising edge of Sclk.
E_WR
Enhancement register write. D[7:0] are latched into the enhancement register
on the rising edge of E_WR.
19
13
Parallel
Direct
Input
Input
Input
Input
Input
A1
A Counter bit1.
M2 write. D[3:0] are latched into the primary register (R[5:4], M[8:7]) on the
rising edge of M2_WR.
M2_WR
A2
Parallel
Direct
20
21
14
15
A Counter bit2.
Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface
Mode (Bmode=0, Smode=0).
Serial,
Parallel
Smode
A3
Direct
ALL
Input
A Counter bit3 (MSB).
16
Bmode
VDD
Selects direct interface mode (Bmode=1).
Same as pin 1 (MLP48 pin 43).
22
23
Input
17,18
ALL
(Note 1)
M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on the
24
25
19
20
M1_WR
A_WR
Parallel
Parallel
Input
Input
rising edge of M1_WR.
A write. D[7:0] are latched into the primary register (R[3:0], A[3:0]) on the
rising edge of A_WR.
Serial,
Parallel
Hop write. The contents of the primary register are latched into the
secondary register on the rising edge of Hop_WR.
26
27
21
22
Hop_WR
Fin
Input
Input
ALL
Prescaler input from the VCO. 3.0 GHz max frequency.
Document No. 70-0049-02 │ www.psemi.com
©2005 Peregrine Semiconductor Corp. All rights reserved.
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