MN3674
•
Timing conditions (without 1-line delay operation) (Ta=0 to + 60˚C)
Parameter
Shift register clock frequency
Reset clock frequency (=data rate)
Shift register clock rise time
Shift register clock fall time
Vertical transfer clock rise time
Vertical transfer clock fall time
Vertical transfer clock pulse width
Shift clock 1 rise time
Shift clock 1 fall time
Shift clock 1 set up time
Shift clock 1 pulse width
Shift clock 2 rise time
Shift clock 2 fall time
Shift clock 2 set up time
Shift clock 2 pulse width
Shift clock 2 hold time
Reset clock rise time
Reset clock fall time
Reset clock set up time
Reset clock pulse width
Reset clock hold time
Symbol
f
C
f
R
t
Cr
t
Cf
t
Vr
t
Vf
t
VW
t
SG1r
t
SG1f
t
SG1s
t
SG1w
t
SG2r
t
SG2f
t
SG2s
t
SG2w
t
SG2h
t
Rr
t
Rf
t
Rs
t
Rw
t
Rh
See drive timing diagram (3)
See drive timing diagram (1)
See drive timing diagram (1)
Condition
See drive timing diagram (3) f
C
=1/2T
See drive timing diagram (3) f
R
=1/2T
See drive timing diagram (3)
ø
SG1
and ø
V
should be the same timing.
See drive timing diagram (1)
CCD Linear Image Sensor
min
0.1
0.1
0
0
0
0
5
0
0
0.5
5
0
0
0.5
5
0
0
0
0.7T
100
10
typ
1.0
1.0
20
20
15
15
10
15
15
1.0
10
15
15
1.0
10
1
10
10
—
200
125
max
3.0
3.0
50
50
50
50
50
50
50
2.0
50
50
50
2.0
50
2
20
20
—
—
—
Unit
MHz
MHz
ns
ns
ns
ns
µs
ns
ns
µs
µs
ns
ns
µs
µs
µs
ns
ns
ns
ns
ns
•
Timing conditions (during 1-line delay operation) (Ta=0 to + 60˚C)
Parameter
Shift register clock frequency
Reset clock frequency (=data rate)
Shift register clock rise time
Shift register clock fall time
Vertical transfer clock rise time
Vertical transfer clock fall time
Vertical transfer clock set up time
Vertical transfer clock pulse width
Vertical transfer clock hold time
Shift clock 1 rise time
Shift clock 1 fall time
Shift clock 1 pulse width
Shift clock 2 rise time
Shift clock 2 fall time
Shift clock 2 set up time
Shift clock 2 pulse width
Reset clock rise time
Reset clock fall time
Reset clock set up time
Reset clock pulse width
Reset clock hold time
Symbol
f
C
f
R
t
Cr
t
Cf
t
Vr
t
Vf
t
Vs
t
Vw
t
Vh
t
SG1r
t
SG1f
t
SG1w
t
SG2r
t
SG2f
t
SG2s
t
SG2w
t
Rr
t
Rf
t
Rs
t
Rw
t
Rh
See drive timing diagram (3)
See drive timing diagram (2)
See drive timing diagram (2)
ø
SG1
and ø
V
should be the same timing.
See drive timing diagram (2)
Condition
See drive timing diagram (3) f
C
=1/2T
See drive timing diagram (3) f
R
=1/2T
See drive timing diagram (3)
min
0.1
0.1
0
0
0
0
0.5
5
0
0
0
5
0
0
0.5
5
0
0
0.7T
100
100
200
125
typ
1.0
1.0
20
20
15
15
1.0
10
1
15
15
10
15
15
1.0
10
10
10
max
3.0
3.0
50
50
50
50
2.0
50
2
50
50
50
50
50
2.0
50
20
20
—
—
—
Unit
MHz
MHz
ns
ns
ns
ns
µs
µs
µs
ns
ns
µs
ns
ns
µs
µs
ns
ns
ns
ns
ns
PANASONIC [ PANASONIC SEMICONDUCTOR ]
