Philips Semiconductors
Product specification
Dual 2-input NOR gate
PACKAGE OUTLINES
74LVC2G02
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
D
E
A
X
c
y
HE
v
M
A
Z
8
5
A
pin 1 index
A2
A1
(A3)
Lp
L
θ
1
e
bp
4
w
M
detail X
0
2.5
scale
5 mm
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A
max.
1.1
A1
0.15
0.00
A2
0.95
0.75
A3
0.25
bp
0.38
0.22
c
0.18
0.08
D
(1)
3.1
2.9
E
(1)
3.1
2.9
e
0.65
HE
4.1
3.9
L
0.5
Lp
0.47
0.33
v
0.2
w
0.13
y
0.1
Z
(1)
0.70
0.35
θ
8°
0°
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
OUTLINE
VERSION
SOT505-2
REFERENCES
IEC
JEDEC
---
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
02-01-16
2004 Sep 15
12
PANASONIC [ PANASONIC SEMICONDUCTOR ]
