Philips Semiconductors
Product specification
Dual 2-input NOR gate
74LVC2G02
TEST CONDITIONS
SYMBOL
PARAMETER
OTHER
T
amb
=
−40 °C
to +125
°C
V
IH
HIGH-level input voltage
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
V
IL
LOW-level input voltage
1.65 to 1.95
2.3 to 2.7
2.7 to 3.6
4.5 to 5.5
V
OH
HIGH-level output
voltage
V
I
= V
IH
or V
IL
I
O
=
−100 µA
I
O
=
−4
mA
I
O
=
−8
mA
I
O
=
−12
mA
I
O
=
−24
mA
I
O
=
−32
mA
V
OL
LOW-level output voltage V
I
= V
IH
or V
IL
I
O
= 100
µA
I
O
= 4 mA
I
O
= 8 mA
I
O
= 12 mA
I
O
= 24 mA
I
O
= 32 mA
I
LI
I
off
I
CC
∆I
CC
Note
1. All typical values are measured at T
amb
= 25
°C.
input leakage current
power OFF leakage
current
V
I
= 5.5 V or GND
V
I
or V
O
= 5.5 V
1.65 to 5.5
1.65
2.3
2.7
3.0
4.5
5.5
0
5.5
2.3 to 5.5
−
−
−
−
−
−
−
−
−
−
1.65 to 5.5
1.65
2.3
2.7
3.0
4.5
V
CC
−
0.1
0.95
1.7
1.9
2.0
3.4
0.65
×
V
CC
1.7
2.0
0.7
×
V
CC
−
−
−
−
V
CC
(V)
MIN.
TYP.
(1)
MAX.
UNIT
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
0.35
×
V
CC
0.7
0.8
0.3
×
V
CC
−
−
−
−
−
−
0.1
0.70
0.45
0.60
0.80
0.80
±20
±20
40
5000
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
quiescent supply current V
I
= V
CC
or GND;
I
O
= 0 A
additional quiescent
supply current per pin
V
I
= V
CC
−
0.6 V;
I
O
= 0 A
2004 Sep 15
8
PANASONIC [ PANASONIC SEMICONDUCTOR ]
