TOP232-234
the MOSFET gate driver. The filtered error signal is compared
with the internal oscillator sawtooth waveform to generate the
dutycyclewaveform. Asthecontrolcurrentincreases, theduty
cycle decreases. A clock signal from the oscillator sets a latch
whichturnsontheoutputMOSFET. Thepulsewidthmodulator
resets the latch, turning off the output MOSFET. Note that a
minimum current must be driven into the CONTROL pin
before the duty cycle begins to change.
136 kHz
Switching
Frequency
128 kHz
4 ms
VDRAIN
The maximum duty cycle, DCMAX,is set at a default maximum
value of 78% (typical). However, by connecting the MULTI-
FUNCTION pin to the rectified DC high voltage bus through a
resistor with appropriate value, the maximum duty cycle can be
made to decrease from 78% to 38% (typical) as shown in
Figure 8 when input line voltage increases (see line feed
forward with DCMAX reduction).
Time
Figure 6. Switching Frequency Jitter.
limit comparator compares the output MOSFET on-state drain
to source voltage, VDS(ON) with a threshold voltage. High drain
current causes VDS(ON) to exceed the threshold voltage and turns
the output MOSFET off until the start of the next clock cycle.
The default current limit of TOPSwitch-FX is preset internally.
However, with a resistor connected between MULTI-
FUNCTION pin and SOURCE pin, current limit can be
programmed externally to a lower level between 40% and
100% of the default current limit. Please refer to the graphs in
thetypicalperformancecharacteristicssectionfortheselection
of the resistor value. By setting current limit low, a
TOPSwitch-FX that is bigger than necessary for the power
required can be used to take advantage of the lower RDS(ON) for
higher efficiency. With a second resistor connected between
the MULTI-FUNCTION pin and the rectified DC high voltage
bus providing a small amount of feed forward current, a true
power limiting operation against line variation can be
implemented. When using an RCD clamp, this feed forward
techniquereducesmaximumclampvoltageathighlineallowing
for higher reflected voltage designs. The current limit
comparator threshold voltage is temperature compensated to
minimize the variation of the current limit due to temperature
related changes in RDS(ON) of the output MOSFET.
Minimum Duty Cycle and Cycle Skipping
To maintain power supply output regulation, the pulse width
modulator reduces duty cycle as the load at the power supply
output decreases. This reduction in duty cycle is proportional
to the current flowing into the CONTROL pin. As the
CONTROLpincurrentincreases,thedutycyclereduceslinearly
towards a minimum value specified as minimum duty cycle,
DCMIN. After reaching DCMIN, if CONTROL pin current is
increased further by approximately 0.4 mA, the pulse width
modulator will force the duty cycle from DCMIN to zero in a
discrete step (refer to Figure 4). This feature allows a power
supply to operate in a cycle skipping mode when the load at its
outputconsumeslesspowerthanthepowerthatTOPSwitch-FX
delivers at minimum duty cycle, DCMIN. No additional control
is needed for the transition between normal operation and cycle
skipping. As the load increases or decreases, the power supply
automatically switches between normal operation and cycle
skipping mode as necessary.
Cycle skipping may be avoided, if so desired, by connecting a
minimum load at the power supply output such that the duty
cycle remains at a level higher than DCMIN at all times.
The leading edge blanking circuit inhibits the current limit
comparator for a short time after the output MOSFET is turned
on. The leading edge blanking time has been set so that, if a
power supply is designed properly, current spikes caused by
primary-side capacitances and secondary-side rectifier reverse
recovery time will not cause premature termination of the
switching pulse.
Error Amplifier
The shunt regulator can also perform the function of an error
amplifierinprimaryfeedbackapplications. Theshuntregulator
voltage is accurately derived from a temperature-compensated
bandgap reference. The gain of the error amplifier is set by the
CONTROL pin dynamic impedance. The CONTROL pin
clamps external circuit signals to the VC voltage level. The
CONTROL pin current in excess of the supply current is
separated by the shunt regulator and flows through RE as a
voltage error signal.
The current limit can be lower for a short period after the
leading edge blanking time as shown in Figure 33. This is due
todynamiccharacteristicsoftheMOSFET. Toavoidtriggering
thecurrentlimitinnormaloperation,thedraincurrentwaveform
should stay within the envelope shown.
On-chip Current Limit with External Programmability
The cycle-by-cycle peak drain current limit circuit uses the
output MOSFET ON-resistance as a sense resistor. A current
Line Under-Voltage Detection (UV)
At power up, UV keeps TOPSwitch-FX off until the input line
B
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PAM [ POWER ANALOG MICOELECTRONICS ]
