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OX16C950-PCC60-B 参数 Datasheet PDF下载

OX16C950-PCC60-B图片预览
型号: OX16C950-PCC60-B
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能UART与128字节的FIFO [High Performance UART with 128 byte FIFOs]
分类和应用: 先进先出芯片
文件页数/大小: 49 页 / 436 K
品牌: OXFORD [ OXFORD SEMICONDUCTOR ]
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OX16C950 rev B  
OXFORD SEMICONDUCTOR LTD.  
PERFORMANCE COMPARISON  
1
Feature  
External 1x baud rate clock  
Max baud rate in normal mode  
Max baud rate in 1x clock mode  
FIFO depth  
OX16C950  
Yes  
15 Mbps  
60 Mbps  
128  
16C450  
No  
115 kbps  
n/a  
1
16C550  
No  
115 kbps  
n/a  
16  
16C650  
No  
1.5 Mbps  
n/a  
32  
16C750  
No  
1 Mbps  
n/a  
64  
Sleep mode  
Auto Xon/Xoff flow  
Yes  
Yes  
Yes  
Yes  
127  
128  
128  
Yes  
Yes  
Yes  
248  
Yes  
No  
No  
No  
No  
1
1
n/a  
No  
n/a  
n/a  
n/a  
No  
No  
No  
No  
No  
4
1
n/a  
No  
No  
Yes  
Yes  
Yes  
No  
4
4
4
No  
No  
No  
Yes  
No  
Yes  
No  
4
1
n/a  
No  
No  
No  
n/a  
No  
Auto CTS#/RTS# flow  
Auto DSR#/DTR# flow  
No. of Rx interrupt thresholds  
No. of Tx interrupt thresholds  
No. of flow control thresholds  
Transmitter empty interrupt  
Readable status of flow control  
Readable FIFO levels  
Clock prescaler options  
Rx/Tx disable  
No  
n/a  
No  
2
No  
Software reset  
Yes  
No  
No  
No  
No  
Device ID  
Yes  
No  
No  
No  
No  
9-bit data frames  
Yes  
No  
No  
No  
No  
RS485 buffer enable  
Infra-red (IrDA)  
Yes  
Yes  
No  
No  
No  
No  
No  
Yes  
No  
No  
Table 1 OX16C950 performance compared with 16C450, 16C550, 16C650 and 16C750 devices  
Improvements of the OX16C950 over previous generations of PC UART:  
Deeper FIFOs:  
OX16C950 offers 128-byte deep FIFOs for the transmitter  
Special character detection:  
and receiver.  
The receiver can be programmed to generate an interrupt  
upon reception of a particular character value.  
Higher data rates:  
Transmission and reception baud rates up to 15Mbps. A  
flexible clock prescaler offers division ratios of 1 to 31 7/8  
in steps of 1/8 using a divide-by-“M N/8” circuitry. The  
flexible prescaler allows users to select from a wide variety  
of input clock frequencies as well as access to higher baud  
rates whilst maintaining compatibility with existing software  
drivers (see section 14.2).  
Power-down:  
The device can be placed in ‘sleep mode’ to conserve  
power.  
Readable FIFO levels:  
Driver efficiency can be improved by using readable FIFO  
levels.  
External clock options:  
Selectable trigger levels:  
The receiver can accept an external 1x clock on the DSR#  
input. The transmitter can accept a 1x clock on the RI#  
input and/or assert its own (Nx) clock on the DTR# output.  
In 1x mode, asynchronous data may be transmitted and  
received at speeds up to 60Mbps (see section 14.6).  
The receiver FIFO threshold can be arbitrarily  
programmed. The transmitter FIFO threshold and  
thresholds for automatic flow control can be programmed  
to operate at a variety of trigger levels.  
Additional control:  
The transmitter and receiver can be independently  
Automatic flow control:  
The UART automatically handles either or both in-band  
(software) flow control (transmitting and receiving Xon/Xoff  
characters) and out-of-band (hardware) flow control using  
the RTS#/CTS# or DSR#/DTR# modem control lines.  
disabled.  
Data Sheet Revision 1.2  
Page 5  
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