OX16C950 rev B
OXFORD SEMICONDUCTOR LTD.
8
TRANSMITTER & RECEIVER FIFOS
Both the transmitter and receiver have associated holding
registers (FIFOs), referred to as the transmitter holding
register (THR) and receiver holding register (RHR)
respectively.
FCR[2]: Flush THR
logic 0 ⇒ No change.
logic 1 ⇒ Flushes the contents of the THR, in the same
manner as FCR[1] does for the RHR.
In normal operation, when the transmitter finishes
transmitting a byte it will remove the next data from the top
of the THR and proceed to transmit it. If the THR is empty,
it will wait until data is written into it. If THR is empty and
the last character being transmitted has been completed
(i.e. the transmitter shift register is empty) the transmitter is
said to be idle. Similarly, when the receiver finishes
receiving a byte, it will transfer it to the bottom of the RHR.
If the RHR is full, an overrun condition will occur (see
section 9.3).
DMA Transfer Signalling:
FCR[3]: DMA signalling mode / Tx trigger level enable
logic 0 ⇒ DMA mode '0'.
logic 1 ⇒ DMA mode '1'.
Note: In DMA mode 0, the transmitter trigger level is
ALWAYS set to 1, thus ignoring FCR[5:4] and TTL.
DMA Control signals can be generated using the TXRDY#
and RXRDY# pins. Their operation is defined as follows:
Data is written into the bottom of the THR queue and read
from the top of the RHR queue completely asynchronously
to the operation of the transmitter and receiver.
The TXRDY# pin has no hysteresis and is simply activated
using a comparison operation. When the UART is in DMA
mode 0 (or in Byte mode), the TXRDY# output pin is active
(low) whenever THR is empty, otherwise it is inactive.
When in DMA mode 1, the TXRDY# pin is inactive (high)
when the THR is full, otherwise it is active, signifying that
there is room in the transmit FIFO.
The size of the FIFOs is dependent on the setting of the
FCR register. When in Byte mode, these FIFOs only
accept one byte at a time before indicating that they are
full; this is compatible with the 16C450. When in a FIFO
mode, the size of the FIFOs is either 16 (compatible with
the 16C550) or 128.
The RXRDY# pin can operate with hysteresis. In DMA
mode 0 (or in Byte mode), RXRDY# is only active (low)
when RHR contains data. When in DMA mode 1 however,
the operation is as follows:
Data written to the THR when it is full is lost. Data read
from the RHR when it is empty is invalid. The empty or full
status of the FIFOs are indicated in the Line Status
Register ‘LSR’ (see section 9.3). Interrupts can be
generated or DMA signals can be used to transfer data
to/from the FIFOs. The number of items in each FIFO may
also be read back from the transmitter FIFO level (TFL)
and receiver FIFO level (RFL) registers (see section 15.2).
1. RXRDY# is set active when RFL has reached the
receiver interrupt trigger level or a time-out event has
occurred (see section 10.3) It remains active as long
as RHR is not empty.
2. RXRDY# is set inactive when RHR is empty. It
remains in this state until condition 1 occurs.
8.1
FIFO Control Register ‘FCR’
FCR[5:4]: THR trigger level
Generally in 450, 550, extended 550 and 950 modes these
bits are unused (see section 5 for mode definition). In 650
mode they define the transmitter interrupt trigger levels and
in 750 mode FCR[5] increases the FIFO size.
FCR[0]: Enable FIFO mode
logic 0 ⇒ Byte mode.
logic 1 ⇒ FIFO mode.
This bit should be enabled before setting the FIFO trigger
levels.
450, 550 and extended 550 modes:
The transmitter interrupt trigger levels are set to 1 and
FCR[5:4] are ignored.
FCR[1]: Flush RHR
logic 0 ⇒ No change.
logic 1 ⇒ Flushes the contents of the RHR
This is only operative when already in a FIFO mode. The
RHR is automatically flushed whenever changing between
Byte mode and a FIFO mode. This bit will return to zero
after clearing the FIFOs.
Data Sheet Revision 1.2
Page 20
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