NCP1236
IP
IP to be
compensated
ILIMIT
High
Line
Low
Line
time
tdelay
tdelay
Figure 38. Line Compensation for True Overpower Protection
To compensate this and have an accurate overpower
protection, an offset proportional to the input voltage is
added on the CS signal by turning on an internal current
source: by adding an external resistor in series between the
sense resistor and the CS pin, a voltage offset is created
across it by the current. The compensation can be adjusted
by changing the value of the resistor.
would be in the same order of magnitude. Therefore the
compensation current is only added when the FB voltage is
higher than V
.
FB(OPCE)
However, because the HV pin can be connected to an ac
voltage, there is needed an additional circuitry to read or at
least closely estimate the actual voltage on the bulk
capacitor.
But this offset is unwanted to appear when the current
sense signal is small, i.e. in light load conditions, where it
S
R
Q
Q
Brown Out
(68 ms)
HV Timer
HV
thv
(32 ms)
Watch
Dog
VHVstop
A/D 3 bit
Converter
+
Peak Detector
3 bit
Register
I Generator
I ctrl
FB
To CS
Block
Tblanking
LEB
CS
VFB(OPC)
Figure 39. Schematic Overpower Compensation Circuit
A 3 bit A/D converter with the peak detector senses the ac
input, and its output is periodically sampled and reset, in
order to follow closely the input voltage variations. The
input. If only the DC high voltage input is used, no reset
signal is generated by the V condition and the 32 ms
watch dog is used to generate the sampling events for
sampling the DC input high voltage line.
HV(stop)
sample and reset events are given by the V
HV(stop)
comparator used for sampling detection for the AC line
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