MC10H166
FIGURE 2
−
25−BIT MAGNITUDE COMPARATOR
B24
A24
B23
A23
B22
A22
B21
A21
B20
A20
B19
A19
B18
A18
B17
A17
B16
A16
B15
A15
B14
A14
B13
A13
B12
A12
B11
A11
B10
A10
B9
A9
B8
A8
B7
A7
B6
A6
A5
B5
B4
A4
B3
A3 A
<
B
B2
A2
B1 A
>
B
A1
B0
A0
B4
A4
B3
A3 A
<
B
B2
A2
B1 A
>
B
A1
B0
A0
B4
A4
B3
A3
B2
A2
B1
A1
B0
A0
B4
A4
B3
A3 A
<
B
B2
A2
B1 A
>
B
A1
B0
A0
A=B
A
<
B
A
>
B
A
<
B
A
>
B
B4
A4
B3
A3
A
<
B
B2
A2
B1
A
>
B
A1
B0
A0
B4
A4
B3
A3 A
<
B2 B
A2
B1
A
>
B
A1
B0
A0
For shorter delay times than possible with serial expansion,
devices can be cascaded. Figure 2 shows a 25−bit cascaded
comparator whose worst case delay is two data−to−output delays.
The cascaded scheme can be extended to longer word lengths.
B4
A4
A3
B2
A2
B1
A1
B0
A0
B3
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