ADT7460
ELECTRICAL CHARACTERISTICS
T
A
= T
MIN
to T
MAX
, V
CC
= V
MIN
to V
MAX
, unless otherwise noted.
Parameter
(Note 1)
DIGITAL INPUT LOGIC LEVELS (THERM)
Input High Voltage, V
IH
Input Low Voltage, V
IL
DIGITAL INPUT CURRENT
Input High Current, I
IH
Input Low Current, I
IL
Input Capacitance, C
IN
SERIAL BUS TIMING
(Note 4)
Clock Frequency, f
SCLK
Glitch Immunity, t
SW
Bus Free Time, t
BUF
Start Setup Time, t
SU;STA
Start Hold Time, t
HD;STA
SCL Low Time, t
LOW
SCL High Time, t
HIGH
SCL, SDA Rise Time, t
R
SCL, SDA Fall Time, t
F
Data Setup Time, t
SU;DAT
Detect Clock Low Timeout, t
TIMEOUT
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
See Figure 2
Can be optionally disabled
100
15
35
1.3
0.6
0.6
1.3
0.6
300
300
400
50
kHz
ns
ms
ms
ms
ms
ms
ns
ms
ns
ms
V
IN
= V
CC
V
IN
= 0
5.0
−1.0
+1.0
mA
mA
pF
1.7
0.8
V
V
Test Conditions/Comments
Min
Typ
(Note 2)
Max
Unit
1. All voltages are measured with respect to GND, unless otherwise specified. Logic inputs accept input high voltages up to V
MAX
even when
the device is operating below V
MIN
. Timing specifications are tested at logic levels of V
IL
= 0.8 V for a falling edge and at V
IH
= 2.0 V for a
rising edge.
2. Typicals are at T
A
= 25°C and represent the most likely parametric norm.
3. The delay is the time between the round robin finishing one set of measurements and starting the next.
4. Guaranteed by design; not production tested
t
LOW
SCL
t
R
t
F
t
HD; STA
t
HIGH
t
HD; STA
t
HD; DAT
t
SU; DAT
t
SU; STA
t
SU; STO
SDA
t
BUF
P
S
S
P
Figure 2. Serial Bus Timing Diagram
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