74HC244
TEST CIRCUITS
TEST POINT
OUTPUT
DEVICE
UNDER
TEST
C
L
*
DEVICE
UNDER
TEST
TEST POINT
OUTPUT
1 kW
CONNECT TO V
CC
WHEN
TESTING t
PLZ
AND t
PZL
.
CONNECT TO GND WHEN
TESTING t
PHZ
AND t
PZH
.
C
L
*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 3. Test Circuit
Figure 4. Test Circuit
PIN DESCRIPTIONS
INPUTS
A1, A2, A3, A4, B1, B2, B3, B4
(Pins 2, 4, 6, 8, 11, 13, 15, 17)
function as noninverting buffers. When a high level is
applied, the outputs assume the high impedance state.
OUTPUTS
YA1, YA2, YA3, YA4, YB1, YB2, YB3, YB4
(Pins 18, 16, 14, 12, 9, 7, 5, 3)
Data input pins. Data on these pins appear in noninverted
form on the corresponding Y outputs, when the outputs are
enabled.
CONTROLS
Enable A, Enable B (Pins 1, 19)
Device outputs. Depending upon the state of the
output−enable pins, these outputs are either noninverting
outputs or high−impedance outputs.
Output enables (active−low). When a low level is applied
to these pins, the outputs are enabled and the devices
LOGIC DETAIL
TO THREE OTHER
A OR B INVERTERS
ONE OF 8
INVERTERS
DATA
INPUT
A OR B
V
CC
YA
OR
YB
ENABLE A OR
ENABLE B
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