74HC244
AC ELECTRICAL CHARACTERISTICS
(C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
Guaranteed Limit
Symbol
t
PLH
,
t
PHL
Parameter
Maximum Propagation Delay, A to YA or B to YB
(Figures 1 and 3)
V
CC
(V)
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
−
−
– 55 to
25_C
96
50
18
15
110
60
22
19
110
60
22
19
60
23
12
10
10
15
v85_C
115
60
23
20
140
70
28
24
140
70
28
24
75
27
15
13
10
15
v125_C
135
70
27
23
165
80
33
28
165
80
33
28
90
32
18
15
10
15
Unit
ns
t
PLZ
,
t
PHZ
Maximum Propagation Delay, Output Enable to YA or YB
(Figures 2 and 4)
ns
t
PZL
,
t
PZH
Maximum Propagation Delay, Output Enable to YA or YB
(Figures 2 and 4)
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 3)
ns
C
in
C
out
Maximum Input Capacitance
Maximum Three−State Output Capacitance
(Output in High−Impedance State)
pF
pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor High−Speed CMOS Data Book (DL129/D).
Typical @ 25°C, V
CC
= 5.0 V
C
PD
Power Dissipation Capacitance (Per Buffer)*
34
pF
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC2
f + I
CC
V
CC
. For load considerations, see Chapter 2 of the
ON Semiconductor High−Speed CMOS Data Book (DL129/D).
SWITCHING WAVEFORMS
t
r
90%
50%
10%
t
PLH
90%
50%
10%
t
TLH
t
PHL
t
f
V
CC
t
PZL
50%
t
PZH
OUTPUT Y
50%
t
PHZ
t
PLZ
10%
90%
GND
HIGH
IMPEDANCE
V
OL
V
OH
HIGH
IMPEDANCE
DATA INPUT
A OR B
OUTPUT
YA OR YB
V
CC
GND
ENABLE
A OR B
50%
OUTPUT Y
t
THL
Figure 1.
Figure 2.
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