74HC138
SWITCHING WAVEFORMS
VALID
INPUT A
t
PLH
OUTPUT Y
50%
50%
t
PHL
OUTPUT Y
t
THL
VALID
V
CC
GND
INPUT CS1
t
PHL
t
r
90%
50%
10%
90%
50%
10%
t
f
V
CC
t
PLH
GND
t
TLH
Figure 1.
Figure 2.
TEST POINT
t
f
INPUT
CS2, CS3
90%
50%
10%
t
r
V
CC
t
PLH
GND
DEVICE
UNDER
TEST
OUTPUT
C
L
*
OUTPUT Y
90%
50%
10%
t
PHL
t
THL
t
TLH
*Includes all probe and jig capacitance
Figure 3.
Figure 4. Test Circuit
PIN DESCRIPTIONS
ADDRESS INPUTS
A0, A1, A2 (Pins 1, 2, 3)
Address inputs. For any other combination of CS1, CS2, and
CS3, the outputs are at a logic high.
OUTPUTS
Y0
−
Y7 (Pins 15, 14, 13, 12, 11, 10, 9, 7)
Address inputs. These inputs, when the chip is selected,
determine which of the eight outputs is active−low.
CONTROL INPUTS
CS1, CS2, CS3 (Pins 6, 4, 5)
Chip select inputs. For CS1 at a high level and CS2, CS3
at a low level, the chip is selected and the outputs follow the
Active−low Decoded outputs. These outputs assume a
low level when addressed and the chip is selected. These
outputs remain high when not addressed or the chip is not
selected.
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