Data Sheet
FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC
Table 13. AC Timing Specifications, Continued
Clock
(MHz)
Parameter
Symbol
Conditions/Description
Min.
Typ.
Max.
Units
Clock Outputs (PLL B clock via CLK_B pin)
Ratio of pulse width (as measured from rising edge
to next falling edge at 2.5V) to one clock period
Duty Cycle*
100
100
45
55
%
On rising edges 500µs apart at 2.5V relative to an
L
XIN
F
ideal clock, C =15pF, f =14.318MHz, N =220,
45
75
R
Px
N =63, N =50, no other PLLs active
y
j(LT)
Jitter, Long Term (σ (τ))*
t
t
ps
On rising edges 500µs apart at 2.5V relative to an
L
XIN
F
ideal clock, C =15pF, f =14.318MHz, N =220,
60
100
60
R
Px
N =63, N =50, all other PLLs active (A=50MHz,
C=40MHz, D=14.318MHz)
From rising edge to the next rising edge at 2.5V,
L
XIN
F
R
Px
C =15pF, f =14.318MHz, N =220, N =63, N =50,
no other PLLs active
120
400
j(∆P)
Jitter, Period (peak-peak)*
ps
From rising edge to the next rising edge at 2.5V,
L
XIN
F
R
Px
C =15pF, f =14.318MHz, N =220, N =63, N =50,
all other PLLs active (A=50MHz, C=40MHz,
D=14.318MHz)
Clock Outputs (PLL_C clock via CLK_C pin)
Ratio of pulse width (as measured from rising edge
to next falling edge at 2.5V) to one clock period
Duty Cycle*
100
100
45
55
%
On rising edges 500µs apart at 2.5V relative to an
L
XIN
F
ideal clock, C =15pF, f =14.318MHz, N =220,
45
R
Px
N =63, N =50, no other PLLs active
y
j(LT)
Jitter, Long Term (σ (τ))*
t
t
ps
On rising edges 500µs apart at 2.5V relative to an
L
XIN
F
ideal clock, C =15pF, f =14.318MHz, N =220,
40
100
40
105
120
440
R
Px
N =63, N =50, all other PLLs active (A=50MHz,
B=60MHz, D=14.318MHz)
From rising edge to the next rising edge at 2.5V,
L
XIN
F
R
Px
C =15pF, f =14.318MHz, N =220, N =63, N =50,
no other PLLs active
j(∆P)
Jitter, Period (peak-peak)*
ps
From rising edge to the next rising edge at 2.5V,
L
XIN
F
R
Px
C =15pF, f =14.318MHz, N =220, N =63, N =50,
all other PLLs active (A=50MHz, B=60MHz,
D=14.318MHz)
Clock Outputs (Crystal Oscillator via CLK_D pin)
Ratio of pulse width (as measured from rising edge
to next falling edge at 2.5V) to one clock period
Duty Cycle*
14.318
14.318
45
55
%
On rising edges 500µs apart at 2.5V relative to an
L
XIN
ideal clock, C =15pF, f =14.318MHz, no other
PLLs active
20
y
j(LT
Jitter, Long Term (σ (τ))*
t
t
ps
From rising edge to the next rising edge at 2.5V,
L
XIN
C =15pF, f =14.318MHz, all other PLLs active
(A=50MHz, B=60MHz, C=40MHz)
14.318
14.318
14.318
40
90
From rising edge to the next rising edge at 2.5V,
L
XIN
C =15pF, f =14.318MHz, no other PLLs active
j(∆P)
Jitter, Period (peak-peak)*
ps
From rising edge to the next rising edge at 2.5V,
L
XIN
C =15pF, f =14.318MHz, all other PLLs active
(A=50MHz, B=60MHz, C=40MHz)
450
DD
A
Unless otherwise stated, V = 5.0V ± 10%, no load on any output, and ambient temperature range T = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal
characterization data and are not currently production tested to any specific limits. Min. and Max. characterization data are ± 3σ from typical.
AMI Semiconductor
www.amis.com
17
ONSEMI [ ONSEMI ]
